D flip-flop having multiplexer function
The present disclosure relates to a D flip-flop having a multiplexer function, including: a first transmission gate whose data input end is configured to receive a first data signal and whose clock input end is configured to receive a first clock signal; a second transmission gate whose data input end is configured to receive a second data signal and whose clock input end is configured to receive a second clock signal; an inverted latch unit whose data input end is connected to an output end of the first transmission gate and an output end of the second transmission gate and whose clock input end is configured to receive a third clock signal; and an inverter whose input end is connected to an output end of the inverted latch unit and whose output end provides an output of the D flip-flop.
1. A D flip-flop with a non-inverted output, the D flip-flop having a multiplexer function, the D flip-flop comprising:
a first transmission gate, a data input end of the first transmission gate being configured to receive a first data signal from external to the D flip-flop, a clock input end of the first transmission gate being configured to receive a first clock signal;
a second transmission gate, a data input end of the second transmission gate being configured to receive a second data signal from external to the D flip-flop, a clock input end of the second transmission gate being configured to receive a second clock signal;
an inverted latch unit, the inverted latch unit having only one data input end that is directly connected to both an output end of the first transmission gate and an output end of the second transmission gate and configured to receive the first data signal from the output end of the first transmission gate or the second data signal from the output end of the second transmission gate, a clock input end of the inverted latch unit being configured to receive a third clock signal, the inverted latch unit having only one output end that is configured to output an inverted first data signal or an inverted second data signal; and
a single inverter, an input end of the single inverter being directly connected to the output end of the inverted latch unit and configured to receive the inverted first data signal or the inverted second data signal from the inverted latch unit, an output end of the single inverter directly providing an output end of the D flip-flop and being configured to output the first data signal or the second data signal,
wherein the first clock signal and the second clock signal cause the first transmission gate and the second transmission gate to be turned on at different times, the third clock signal causes the inverted latch unit to be turned off when one of the first transmission gate and the second transmission gate is turned on and to be turned on when both the first transmission gate and the second transmission gate are turned off,
wherein each of the first clock signal, the second clock signal, and the third clock signal comprises signals having opposite phases,
wherein,
an in-phase signal of the first clock signal is obtained by performing an AND operation on a common clock signal and one of a selection signal and an inverted selection signal, an inverted signal of the first clock signal is obtained by performing a NOT operation on the in-phase signal of the first clock signal,
an in-phase signal of the second clock signal is obtained by performing an AND operation on the common clock signal and the other one of the selection signal and the inverted selection signal, an inverted signal of the second clock signal is obtained by performing a NOT operation on the in-phase signal of the second clock signal,
an in-phase signal of the third clock signal is the common clock signal, an inverted signal of the third clock signal is obtained by performing a NOT operation on the common clock signal.
2. The D flip-flop according to claim 1 , wherein the inverted latch unit is one of:
a first tri-state gate; or
a second inverter and a third transmission gate connected in series.
3. The D flip-flop according to claim 1 , further comprising an inverted feedback unit, a data input end of the inverted feedback unit being connected to the output end of the inverter, an output end of the inverted feedback unit being connected to the input end of the inverter, a clock input end of the inverted feedback unit being configured to receive a fourth clock signal,
wherein the fourth clock signal causes the inverted feedback unit to be turned off when the inverted latch unit is turned on and to be turned on when the inverted latch unit is turned off.
4. The D flip-flop according to claim 3 , wherein the inverted feedback unit is one of:
a second tri-state gate; or
a third inverter and a fourth transmission gate connected in series.
5. The D flip-flop according to claim 3 , wherein, the fourth clock signal comprises signals having opposite phases.
6. The D flip-flop according to claim 5 , wherein an in-phase signal of the fourth clock signal is the common clock signal, an inverted signal of the fourth clock signal is obtained by performing a NOT operation on the common clock signal.
7. An arithmetic circuit comprising a plurality of D flip-flops according to claim 3 .
8. The arithmetic circuit according to claim 7 , further comprising:
a fourth inverter, an input of the fourth inverter being configured to receive the selection signal and output the inverted selection signal;
a first clock signal generator configured to receive the common clock signal and the one of the selection signal and the inverted selection signal outputted by the fourth inverter and output the first clock signal;
a second clock signal generator configured to receive the common clock signal and the other one of the selection signal and the inverted selection signal outputted by the fourth inverter and output the second clock signal; and
a third clock signal generator configured to receive the common clock signal and output the third clock signal and the fourth clock signal.
9. The D flip-flop according to claim 1 , wherein one of the first data signal and the second data signal is a functional data signal, the other one of the first data signal and the second data signal is a scan data signal.
10. An arithmetic circuit comprising a plurality of D flip-flops according to claim 1 .
11. The arithmetic circuit according to claim 10 , further comprising:
a fourth inverter, an input of the fourth inverter being configured to receive the selection signal and output the inverted selection signal;
a first clock signal generator configured to receive the common clock signal and the one of the selection signal and the inverted selection signal outputted by the fourth inverter and output the first clock signal;
a second clock signal generator configured to receive the common clock signal and the other one of the selection signal and the inverted selection signal outputted by the fourth inverter and output the second clock signal; and
a third clock signal generator configured to receive the common clock signal and output the third clock signal.
12. A processor comprising an arithmetic circuit that comprises a plurality of D flip-flops according to claim 1 .