MIS capacitor and method of making a MIS capacitor
A MIS capacitor and a method of making the same. The capacitor includes a semiconductor substrate having a first part having a first conductivity type and contact regions for coupling the first part to an output node. The substrate has dielectric on a surface of the first part and electrodes on the dielectric. The substrate has a second part having a second conductivity type and a third part having the first conductivity type. The third part is coupleable to a supply voltage. The second part is located between the first part and the third part. The first part and the second part form a first p-n junction and the second part and the third part form a second p-n junction. A reference contact is provided for coupling the second part to a reference voltage. A further contact region is provided for coupling the second part to the output node.
1. A Metal Insulator Semiconductor, “MIS”, capacitor comprising:
a semiconductor substrate comprising:
a first part having a first conductivity type;
a plurality of contact regions located in the first part for coupling the first part to an output node;
dielectric located on a surface of the first part;
a plurality of electrodes separated from the first part by the dielectric;
a second part having a second conductivity type; and
a third part having the first conductivity type, wherein the third part is coupleable to a supply voltage, wherein the second part is located between the first part and the third part, wherein the first part and the second part form a first p-n junction and wherein the second part and the third part form a second p-n junction;
a reference contact for coupling the second part to a reference voltage; and
a further contact region for coupling the second part to the output node.
2. The MIS capacitor of claim 1 , wherein an orientation of the first p-n junction within the substrate is opposite to an orientation of the second p-n junction within the substrate.
3. The MIS capacitor of claim 2 , wherein a reverse bias leakage current of the first p-n junction at least partially cancels a reverse bias leakage current of the second p-n junction.
4. The MIS capacitor of claim 3 , wherein the reverse bias leakage current of the first p-n junction is substantially equal to the reverse bias leakage current of the second p-n junction.
5. The MIS capacitor of claim 1 , further comprising a first well region having the second conductivity type, wherein the first well region is located between the reference contact and the second part.
6. The MIS capacitor of claim 1 , further comprising a second well region having the second conductivity type, wherein the second well region is located between the further contact region and the second part.
7. The MIS capacitor of claim 1 , wherein the first part, the second part and the third part each comprise a well or layer of semiconductor material located in the semiconductor substrate.
8. The MIS capacitor of claim 1 , wherein the first conductivity type is n-type conductivity and wherein the second conductivity type is p-type conductivity.
9. The MIS capacitor of claim 1 , wherein the reference voltage is ground.
10. An amplifier circuit including a Metal Insulator Semiconductor, “MIS”, capacitor, the MIS capacitor comprising:
a semiconductor substrate comprising:
a first part having a first conductivity type;
a plurality of contact regions located in the first part for coupling the first part to an output node;
dielectric located on a surface of the first part;
a plurality of electrodes separated from the first part by the dielectric;
a second part having a second conductivity type; and
a third part having the first conductivity type, wherein the third part is coupleable to a supply voltage, wherein the second part is located between the first part and the third part, wherein the first part and the second part form a first p-n junction and wherein the second part and the third part form a second p-n junction;
a reference contact for coupling the second part to a reference voltage; and
a further contact region for coupling the second part to the output node.
11. The amplifier circuit of claim 10 , comprising:
a first amplifier stage; and
a second amplifier stage having an input coupled to an output of the first amplifier stage, wherein the MIS capacitor is coupled in parallel with the second amplifier stage.
12. The amplifier circuit of claim 11 , wherein the first amplifier stage comprises a differential amplifier comprising:
a first input coupled to a reference voltage; and
a second input coupled to receive an output of the second amplifier stage via a feedback network.
13. The amplifier circuit of claim 11 , wherein the output node of the MIS capacitor is coupled to the input of the second amplifier stage and to the output of the first amplifier stage.
14. The amplifier circuit of claim 10 , wherein an orientation of the first p-n junction within the substrate is opposite to an orientation of the second p-n junction within the substrate.
15. The amplifier circuit of claim 14 , wherein a reverse bias leakage current of the first p-n junction at least partially cancels a reverse bias leakage current of the second p-n junction.
16. The amplifier circuit of claim 15 , wherein the reverse bias leakage current of the first p-n junction is substantially equal to the reverse bias leakage current of the second p-n junction.
17. The amplifier circuit of claim 10 , further comprising a first well region having the second conductivity type, wherein the first well region is located between the reference contact and the second part.
18. The amplifier circuit of claim 10 , further comprising a second well region having the second conductivity type, wherein the second well region is located between the further contact region and the second part.
19. The amplifier circuit of claim 10 , wherein the first part, the second part and the third part each comprise a well or layer of semiconductor material located in the semiconductor substrate.
20. A method of making a Metal Insulator Semiconductor, “MIS”, capacitor, the method comprising:
forming a semiconductor substrate comprising:
a first part having a first conductivity type;
a second part having a second conductivity type; and
a third part having the first conductivity type, wherein the third part is coupleable to a supply voltage, wherein the second part is located between the first part and the third part, wherein the first part and the second part form a first p-n junction and wherein the second part and the third part form a second p-n junction;
forming a plurality of contact regions in the first part for coupling the first part to an output node;
forming dielectric on a surface of the first part;
forming a plurality of electrodes on the dielectric, wherein the plurality of electrodes are separated from the first part by the dielectric;
forming a reference contact for coupling the second part to a reference voltage; and
forming a further contact region for coupling the second part to the output node.