Method of manufacturing a semiconductor device and a semiconductor device
View Patent ↗In a method of manufacturing a semiconductor device, first and second fin structures are formed over a substrate, an isolation insulating layer is formed over the substrate, a gate structure is formed over channel regions of the first and second fin structures, source/drain regions of the first and second fin structure are recessed, and an epitaxial source/drain structure is formed over the recessed first and second fin structures. The epitaxial source/drain structure is a merged structure having a merger point, and a height of a bottom of the merger point from an upper surface of the isolation insulating layer is 50% or more of a height of the channel regions of the first and second fin structures from the upper surface of the isolation insulating layer.
1. A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer over a substrate;
forming a sacrificial layer over the gate dielectric layer;
patterning the sacrificial layer to form a sacrificial gate electrode;
forming a plurality of openings in the sacrificial gate electrodes by partially etching the sacrificial gate electrode;
filling the plurality of openings with a filling material different from a material of the sacrificial gate electrode;
removing the sacrificial gate electrode to form a gate space, thereby leaving a plurality of pillars or walls in the gate space;
filling the gate space with one or more conductive materials, thereby forming a metal gate electrode; and
forming sidewall spacers on sidewalls of the sacrificial gate electrode,
wherein the plurality of pillars or walls are located between a pair of the sidewall spacers in a cross section, and the pillars or walls penetrate through the metal gate electrode.
2. The method of claim 1 , wherein the sacrificial gate electrode includes polysilicon or amorphous silicon.
3. The method of claim 1 , wherein the filling material is a dielectric material.
4. The method of claim 3 , wherein the filling material includes one or more of silicon oxide, silicon nitride, SiON, SiOC, SiOCN or SiCN.
5. The method of claim 1 , further comprising forming a cap layer made of a conductive material over the gate dielectric layer before the sacrificial layer is formed,
wherein the plurality of pillars or walls and the one or more conductive materials are formed over the cap layer.
6. The method of claim 1 , wherein the sidewall spacers are formed on the sidewalls of the sacrificial gate electrode before the plurality of openings are formed.
7. The method of claim 1 , wherein the sidewall spacers are formed on the sidewalls of the sacrificial gate electrode after the plurality of openings are formed.
8. The method of claim 7 , wherein the plurality of pillars or walls includes a bottom layer made of a same material as the sidewall spacers, and an upper layer made of the filling material.
9. The method of claim 1 , wherein the filling the gate space with the one or more conductive materials comprises:
forming a blanket layer of the one or more conductive materials; and
performing a chemical mechanical polishing (CMP) operation on the one or more conductive materials,
wherein the CMP operation stops at the plurality of pillars or walls.
10. The method of claim 1 , wherein the metal gate electrode has a width W and length L in plan view and a gate area W×L is equal to or more than 3 μm 2 .
11. The method of claim 10 , wherein a total area of the plurality of pillars or walls in plan view is 1% to 25% of the gate area.
12. A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer over a substrate;
forming a sacrificial layer over the gate dielectric layer;
patterning the sacrificial layer to form a sacrificial gate electrode;
forming sidewall spacers on sidewalls of the sacrificial gate electrode as seen in a cross section;
forming an interlayer dielectric layer over the sidewall spacers;
patterning the sacrificial gate electrode, thereby forming a plurality of pillars or walls in a gate space between a pair of the sidewall spacers;
forming one or more conductive layers in the gate space and over the interlayer dielectric layer; and
performing a chemical mechanical polishing on the one or more conductive layers, thereby forming a metal gate electrode,
wherein the plurality of pillars or walls extend through an entire thickness of the one or more conductive layers.
13. The method of claim 12 , further comprising forming a cap layer made of a conductive material over the gate dielectric layer before the sacrificial layer is formed,
wherein the plurality of pillars or walls are formed over the cap layer.
14. The method of claim 13 , wherein the cap layer is made of TiN.
15. The method of claim 12 , wherein the plurality of pillars or walls are made of polysilicon.
16. The method of claim 12 , wherein an area of each of the plurality of pillars or wall in plan view is in a range from 0.01 μm 2 to 1.0 μm 2 .
17. The method of claim 12 , wherein:
the gate electrode has a width W and length L in plan view and a gate area W×L is equal to or more than 5 μm 2 , and
a total area of the plurality of pillars or walls in plan view is 1% to 25% of the gate area.
18. A method of manufacturing a semiconductor device, comprising:
forming a gate dielectric layer over a substrate;
forming a sacrificial layer over the gate dielectric layer;
patterning the sacrificial layer to form a first sacrificial gate electrode and a second sacrificial gate electrode;
forming a sidewall spacer on a sidewall of each of the first and second sacrificial gate electrodes;
forming an interlayer dielectric layer over the sidewall spacer;
removing the first sacrificial gate electrode, thereby forming a first gate space and patterning the second sacrificial gate electrode, thereby forming a plurality of pillars or walls between a pair of sidewall spacers in a cross section in a second gate space;
forming one or more conductive layers in the first and second gate spaces and over the interlayer dielectric layer; and
performing a chemical mechanical polishing on the one or more conductive layers, thereby forming a first metal gate electrode with no pillar or wall and a second metal gate electrode with the plurality of pillars or walls,
wherein the plurality of pillars or walls extend through an entire thickness of the second metal gate electrode.
19. The method of claim 18 , wherein a gate length of the first metal gate electrode is smaller than a gate length of the second metal gate electrode.
20. The method of claim 18 , wherein:
an area of the first metal gate electrode in plan view is smaller than an area of the second metal gate electrode in plan view, and
the area of the second metal gate electrode is equal to or more than 3 μm 2 .