Indirect branch predictor storing encrypted branch information fields
A system and method for efficiently protecting branch prediction information. In various embodiments, a computing system includes at least one processor with a branch predictor storing branch target addresses and security tags in a table. The security tag includes one or more components of machine context. When the branch predictor receives a portion of a first program counter of a first branch instruction, and hits on a first table entry during an access, the branch predictor reads out a first security tag. The branch predictor compares one or more components of machine context of the first security tag to one or more components of machine context of the first branch instruction. When there is at least one mismatch, the branch prediction information of the first table entry is not used. Additionally, there is no updating of any branch prediction training information of the first table entry.
1. An apparatus, comprising:
a table comprising circuitry, wherein the table comprises a plurality of table entries configured to store branch prediction information; and
branch prediction circuitry configured to:
generate an encrypted value, based at least in part on a program counter corresponding to a branch instruction;
combine, using encryption circuitry, the encrypted value with a branch target address of the branch instruction to generate an encrypted branch target address; and
store the encrypted branch target address in an entry of the table.
2. The apparatus as recited in claim 1 , wherein the branch prediction circuitry is configured to store machine context information corresponding to the branch instruction in the entry.
3. The apparatus as recited in claim 2 , wherein the branch prediction circuitry is configured to store the machine context information as a security tag in a security tag field of the entry.
4. The apparatus as recited in claim 2 , wherein the branch prediction circuitry is further configured generate the machine context information based at least in part on one or more of an exception level, virtual machine identifier, privilege mode, process identifier, and a program counter.
5. The apparatus as recited in claim 2 , wherein the branch prediction circuitry is configured to:
detect a hit on the entry in the table, responsive to a first branch instruction; and
prevent use of branch prediction information in the entry by the first branch instruction, responsive to a mismatch between at least a portion of a machine context of the first branch instruction and machine context information stored in the entry.
6. The apparatus as recited in claim 5 , wherein the apparatus is configured to generate an exception responsive to the mismatch.
7. The apparatus as recited in claim 5 , wherein the branch prediction circuitry is configured to allow use of the branch prediction information in the entry by the first branch instruction, responsive to a match between the machine context of the first branch instruction and the machine context information stored in the entry.
8. The apparatus as recited in claim 7 , wherein the branch prediction circuitry is configured to update branch prediction training information stored in the entry, responsive to the match between the machine context of the first branch instruction and the machine context information stored in the entry.
9. A method, comprising:
generating an encrypted value, based at least in part on a program counter corresponding to a branch instruction;
combining the encrypted value with a branch target address of the branch instruction to generate an encrypted branch target address; and
storing the encrypted branch target address in an entry of a table.
10. The method as recited in claim 9 , further comprising storing machine context information corresponding to the branch instruction in the entry.
11. The method as recited in claim 10 , further comprising storing the machine context information as a security tag in a security tag field of the entry.
12. The method as recited in claim 10 , further comprising generating the machine context information based at least in part on one or more of an exception level, virtual machine identifier, privilege mode, process identifier, and a program counter.
13. The method as recited in claim 10 , further comprising:
detecting a hit on the entry in the table, responsive to a first branch instruction; and
preventing use of branch prediction information in the entry by the first branch instruction, responsive to a mismatch between at least a portion of a machine context of the first branch instruction and machine context information stored in the entry.
14. The method as recited in claim 13 , further comprising generating an exception responsive to the mismatch.
15. The method as recited in claim 13 , further comprising allowing use of the branch prediction information in the entry by the first branch instruction, responsive to a match between the machine context of the first branch instruction and the machine context information stored in the entry.
16. The method as recited in claim 15 , further comprising updating branch prediction training information stored in the entry, responsive to the match between the machine context of the first branch instruction and the machine context information stored in the entry.
17. A processor, comprising:
instruction fetch circuitry configured to fetch instructions for execution;
execution circuitry configured to execute instructions fetched by the instruction fetch circuitry; and
branch prediction circuitry configured to:
generate an encrypted value, based at least in part on a program counter corresponding to a branch instruction;
combine, using encryption circuitry, the encrypted value with a branch target address of the branch instruction to generate an encrypted branch target address; and
store the encrypted branch target address in an entry of a table.
18. The processor as recited in claim 17 , wherein the branch prediction circuitry is configured to store machine context information corresponding to the branch instruction in the entry.
19. The processor as recited in claim 18 , wherein the branch prediction circuitry is configured to:
detect a hit on the entry in the table, responsive to a first branch instruction; and
prevent use of branch prediction information in the entry by the first branch instruction, responsive to a mismatch between at least a portion of a machine context of the first branch instruction and machine context information stored in the entry.
20. The processor as recited in claim 19 , wherein the branch prediction circuitry is configured to allow use of the branch prediction information in the entry by the first branch instruction, responsive to a match between the machine context of the first branch instruction and the machine context information stored in the entry.