Cache-line retention hint information for conditional write instruction
In response to instruction decoding circuitry decoding a conditional write instruction, processing circuitry determines whether a predetermined condition is satisfied for a target cache line corresponding to a target address specified by the conditional write instruction. If the predetermined condition is satisfied for the target cache line, a write request is issued to update the target cache line. If the predetermined condition is not satisfied for the target cache line, a failure indication is returned. The processing circuitry selects, depending on whether the sequence of instructions specifies cache-line-retention hint information applicable to the conditional write instruction, whether to prevent a unique coherency state of the target cache line being relinquished by a local cache associated with the processing circuitry for a retention period following processing of the conditional write instruction. The unique coherency state comprises a coherency state in which the processing circuitry has exclusive right to update the target cache line.
1. An apparatus comprising:
instruction decoding circuitry to decode a sequence of instructions; and
processing circuitry to perform data processing in response to decoding of the sequence of instructions by the instruction decoding circuitry; in which:
in response to the instruction decoding circuitry decoding a conditional write instruction, the processing circuitry is configured to:
determine whether a predetermined condition is satisfied for a target cache line corresponding to a target address specified by the conditional write instruction;
in response to determining that the predetermined condition is satisfied for the target cache line, issue a write request to update the target cache line; and
in response to determining that the predetermined condition is not satisfied for the target cache line, return a failure indication; and
select, depending on whether the sequence of instructions specifies cache-line-retention hint information applicable to the conditional write instruction, whether to prevent a unique coherency state of the target cache line being relinquished by a local cache associated with the processing circuitry for a retention period following processing of the conditional write instruction, the unique coherency state comprising a coherency state in which the processing circuitry has exclusive right to update the target cache line.
2. The apparatus according to claim 1 , in which the conditional write instruction comprises a compare-and-swap instruction specifying the target address, a compare operand and a swap operand;
the processing circuitry is configured to determine whether the predetermined condition is satisfied based on a comparison of the compare operand with a value loaded for the target cache line; and
in response to determining that the predetermined condition is satisfied, the processing circuitry is configured to issue the write request to write the swap operand to the target cache line.
3. The apparatus according to claim 2 , in which, at least when the conditional write instruction comprises the compare-and-swap instruction for which the compare operand differs from the swap operand, the processing circuitry is configured to determine that the cache-line-retention hint information is applicable to the conditional write instruction when the predetermined condition is not satisfied for the conditional write instruction, but determine that the cache-line-retention hint information is not applicable to the conditional write instruction when the predetermined condition is satisfied for the conditional write instruction.
4. The apparatus according to claim 1 , in which during the retention period, the processing circuitry is configured to prevent the unique coherency state of the target cache line being relinquished by delaying responding to snoop requests relating to the target cache line until after the end of the retention period.
5. The apparatus according to claim 1 , in which at least one of the instruction decoding circuitry and the processing circuitry is configured to detect whether the sequence of instructions specifies the cache-line-retention hint information based on whether the conditional write instruction specifies the cache-line-retention hint information.
6. The apparatus according to claim 1 , in which at least one of the instruction decoding circuitry and the processing circuitry is configured to detect whether the sequence of instructions specifies the cache-line-retention hint information based on whether an earlier instruction than the conditional write instruction specifies the cache-line-retention hint information.
7. The apparatus according to claim 6 , in which:
in response to decoding of a compare-and-swap instruction specifying a given address, a compare operand and a swap operand, the processing circuitry is configured to compare the compare operand with a value loaded for a given cache line corresponding to the given address, and in response to determining that a comparison condition is satisfied, write the swap operand to a given cache line corresponding to the given address; and
the earlier instruction comprises an instance of the compare-and-swap instruction for which the compare operand equals the swap operand.
8. The apparatus according to claim 7 , in which the cache-line-retention hint information is applicable to the conditional write instruction when the earlier instruction specifies the cache-line-retention hint information and no instance of a hint-cancelling event has occurred between the earlier instruction and the conditional write instruction.
9. The apparatus according to claim 8 , in which the hint-cancelling event comprises one of:
an exception being taken;
the predetermined condition being determined to be satisfied for another conditional write instruction occurring between the earlier instruction and the conditional write instruction;
another conditional write instruction being detected as specifying an address of a different cache line to the target cache line;
eviction of the target cache line from the local cache; or
a hardware counter timeout event.
10. The apparatus according to claim 1 , in which the processing circuitry is configured to determine whether the cache-line-retention hint information is applicable to the conditional write instruction depending on whether at least one applicability condition specified by the cache-line-retention hint information is satisfied for the conditional write instruction.
11. The apparatus according to claim 10 , in which the at least one applicability condition specifies a threshold number of intervening instructions; and
the processing circuitry is configured to determine that the cache-line-retention hint information is not applicable to the conditional write instruction when a number of intervening instructions between an earlier instruction specifying the cache-line-retention hint information and the conditional write instruction is greater than the threshold number.
12. The apparatus according to claim 10 , in which the at least one applicability condition specifies at least one branch outcome condition; and
the processing circuitry is configured to determine that the cache-line-retention hint information is not applicable to the conditional write instruction when a pattern of branch outcomes of one or more branch instructions preceding the conditional write instruction fail to satisfy the at least one branch outcome condition.
13. The apparatus according to claim 1 , in which the processing circuitry is configured to end the retention period in response to a hardware counter timeout event occurring after processing of the conditional write instruction.
14. The apparatus according to claim 1 , in which the processing circuitry is configured to end the retention period after elapse of a period of variable duration selected based on retention period duration information specified by the cache-line-retention hint information.
15. The apparatus according to claim 1 , in which the processing circuitry is configured to end the retention period in response to occurrence of a retention period reset event.
16. The apparatus according to claim 15 , in which the retention period reset event comprises one of:
an exception being taken;
the predetermined condition being determined to be satisfied for another conditional write instruction occurring after the conditional write instruction;
another conditional write instruction being detected as specifying an address of a different cache line to the target cache line;
eviction of the target cache line from the local cache; or
a hardware counter timeout event.
17. The apparatus according to claim 1 , in which the processing circuitry is configured to provide a retention hint signal to coherency control circuitry responsible for managing coherency between the local cache and a further cache, the retention hint signal indicating that the local cache would not relinquish the unique coherency state during the retention period.
18. A non-transitory computer-readable medium to store computer-readable code for fabrication of an apparatus comprising:
instruction decoding circuitry to decode a sequence of instructions; and
processing circuitry to perform data processing in response to decoding of the sequence of instructions by the instruction decoding circuitry; in which:
in response to the instruction decoding circuitry decoding a conditional write instruction, the processing circuitry is configured to:
determine whether a predetermined condition is satisfied for a target cache line corresponding to a target address specified by the conditional write instruction;
in response to determining that the predetermined condition is satisfied for the target cache line, issue a write request to update the target cache line; and
in response to determining that the predetermined condition is not satisfied for the target cache line, return a failure indication; and
select, depending on whether the sequence of instructions specifies cache-line-retention hint information applicable to the conditional write instruction, whether to prevent a unique coherency state of the target cache line being relinquished by a local cache associated with the processing circuitry for a retention period following processing of the conditional write instruction, the unique coherency state comprising a coherency state in which the processing circuitry has exclusive right to update the target cache line.
19. A method comprising:
decoding a sequence of instructions; and
in response to decoding of the sequence of instructions, performing data processing using processing circuitry; in which:
in response to decoding of a conditional write instruction, the data processing comprises:
determining whether a predetermined condition is satisfied for a target cache line corresponding to a target address specified by the conditional write instruction;
in response to determining that the predetermined condition is satisfied for the target cache line, issuing a write request to update the target cache line; and
in response to determining that the predetermined condition is not satisfied for the target cache line, returning a failure indication; and
selecting, depending on whether the sequence of instructions specifies cache-line-retention hint information applicable to the conditional write instruction, whether to prevent a unique coherency state of the target cache line being relinquished by a local cache associated with the processing circuitry for a retention period following processing of the conditional write instruction, the unique coherency state comprising a coherency state in which the processing circuitry has exclusive right to update the target cache line.