Reducing link up time in PCIe systems
The present disclosure generally relates to reducing link-up time between an upstream device and a downstream device. Rather than re-coordinating the link between devices each time, knowledge gained from a previous link-up is used to speed up the link-up. Typically, when both the upstream device and the downstream device have not changed, then the coefficient values for downstream port (DSP) transmission (Tx) equilibrium (EQ) that resulted in a desired bit error rate (BER) should not have changed either. Hence, rather than exchanging coefficients, the previous values can be reused with confidence eliminating the need to exchange coefficients. In so doing, the link-up process is much faster and system resources are not wasted on unnecessary coefficient exchanges.
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller is configured to:
send a speed change request to a host device;
determine that optimal channel setup values do not exist for link-up between the host device and the data storage device;
perform channel setup and determine the optimal channel setup values;
record the optimal channel setup values in a table;
send a speed change request to the host device; and
perform channel setup using the recorded optimal channel setup values.
2. The data storage device of claim 1 , wherein the link-up is over a peripheral component interface express (PCIe) bus.
3. The data storage device of claim 1 , wherein performing channel setup comprises proceeding through Phase 0, Phase 1, Phase 2, and Phase 3 to verify bit error rate (BER) suitability.
4. The data storage device of claim 3 , wherein:
in Phase 0, the host device reports presets for a particular speed and verifies the BER;
in Phase 1 the controller verifies BER and indicates moving to Phase 2;
in Phase 2 the host device sends coefficient values to adjust downstream port (DSP) transmission (Tx) equilibrium (Eq) until achieving a predetermined BER; and
in Phase 3, the controller sends coefficient values to adjust upstream (USP) Tx Eq until the achieving the predetermined BER.
5. The data storage device of claim 4 , in Phase 1, wherein performing channel setup using the recorded optimal channel setup values comprises skipping Phase 2 and Phase 3.
6. The data storage device of claim 5 , wherein the verified BER in Phase O and Phase 1 is less than 10 −4 .
7. The data storage device of claim 6 , wherein the predetermined BER in Phase 2 and Phase 3 is less than 10 −12 .
8. The data storage device of claim 1 , wherein the controller is configured to:
determine that optimal channel setup values cease to be sufficient;
perform a full negotiation and update the optimal channel setup values; and
record updated optimal channel setup values in a table.
9. The data storage device of claim 8 , wherein the memory device comprises one or more volatile memory devices.
10. The data storage device of claim 8 , wherein performing channel setup comprises proceeding sequential phases, wherein:
Phase 0, wherein the host device reports presets for a particular speed and verifies bit error rate (BER) of less than a first threshold value;
Phase 1, wherein the controller verifies reliable lane operation by the BER of less than the first threshold value;
Phase 2, wherein the host device sends coefficient values to adjust DSP Tx Eq until the BER is less than a second threshold value; and
Phase 3, wherein the controller sends coefficient values to adjust upstream (USP) Tx Eq until achieving the BER of less than the second threshold value.
11. The data storage device of claim 10 , wherein the controller device indicates completion of Phase 0, Phase 1, and Phase 3, and a move to the subsequent phase, wherein Phase 0 is subsequent to Phase 3.
12. The data storage device of claim 11 , wherein the host device indicates completion of Phase 2, and a move to Phase 3.
13. The data storage device of claim 10 , wherein the first threshold value is 10 −4 , wherein the second threshold value is 10 −12 .
14. The data storage device of claim 10 , wherein sufficient verification of BER, in Phase 0, comprises skipping Phase 1 and Phase 2.
15. The data storage device of claim 8 , wherein the recorded optimal channel setup values change over time.
16. The data storage device of claim 15 , wherein the device performs the full negotiation, wherein the full negotiation comprises completion of Phase 2 and Phase 3.
17. The data storage device of claim 8 , wherein the table is preloaded to the controller, wherein the table is dynamic.
18. The data storage device of claim 1 , wherein the controller is configured to:
determine whether optimum channel setup values exist for a particular channel in response to the speed change request; and
implement the optimum channel setup values, wherein the implementing occurs without searching for the optimum channel setup values.
19. The data storage device of claim 18 , wherein the controller is configured to send the optimum channel setup values to a downstream device.
20. The data storage device of claim 18 , wherein the determining and implementing occurs during a recovery state.