Systems, methods, and devices for advanced memory technology
An electronic device includes a processor having processor circuitry and a leader memory controller, a controller coupled to the processor and having a follower memory controller, and a memory. The processor circuitry is operable to access the memory by issuing memory access requests to the leader memory controller. The leader memory controller is operable to complete the memory access requests using the follower memory controller to issue memory commands to the at least one memory die.
1. An electronic device, comprising:
a processor having processor circuitry and a leader memory controller;
a controller coupled to the processor and having a follower memory controller; and
a memory,
wherein the processor circuitry is operable to generate memory access requests to the leader memory controller, and the leader memory controller is operable to schedule an order of the memory access requests, wherein the leader memory controller is operable to provide a sequence of the memory access requests in the order to the follower memory controller, and the follower memory controller is operable to issue the sequence of the memory access requests to the memory.
2. The electronic device of claim 1 , wherein:
the processor is implemented on a processor die;
the controller is implemented on a controller die; and
the memory is implemented on at least one memory die.
3. The electronic device of claim 2 , wherein:
the processor die comprises a first major surface and a second major surface; and
the controller die comprises a first major surface and a second major surface by which the controller die is mounted on the first major surface of the processor die and the follower memory controller is electrically coupled to the leader memory controller; and
the at least one memory die is mounted on the first major surface of the controller die and each of the at least one memory die is electrically coupled to the follower memory controller.
4. The electronic device of claim 3 , wherein:
the at least one memory die comprises one of: at least one stacked dynamic random access memory (DRAM) die, at least one embedded DRAM die, at least one ferro-electric random access memory (FeRAM) die, at least one spin-torque transfer memory die, at least one magneto-resistive memory die, and at least one phase-change memory die.
5. The electronic device of claim 1 , wherein:
wherein the leader memory controller and the follower memory controller together issue commands received by the leader memory controller to the memory in an order different from an order provided by the processor circuitry based on a plurality of predetermined criteria.
6. The electronic device of claim 5 , wherein:
the plurality of predetermined criteria includes a respective quality-of-service indicator, and the leader memory controller sends the respective quality-of-service indicator with each memory access request to the follower memory controller.
7. The electronic device of claim 5 , wherein the leader memory controller comprises:
a command queue for storing memory access requests;
a page table for storing a current page state of memory pages in the memory; and
a picker for selecting entries from the command queue based on the plurality of predetermined criteria and providing selected entries with a corresponding page state from the page table to the follower memory controller.
8. The electronic device of claim 7 , wherein:
the follower memory controller issues row commands selectively in response to the current page state of a corresponding memory page provided by the leader memory controller.
9. The electronic device of claim 1 , wherein:
the leader memory controller and the follower memory controller are optically connected.
10. The electronic device of claim 1 , wherein the follower memory controller comprises:
a first follower memory controller having a first command queue for storing memory access requests from the leader memory controller to a first pseudo-channel of the memory; and
a second follower memory controller having a second command queue for storing memory access requests from the leader memory controller to a second pseudo-channel of the memory.
11. The electronic device of claim 1 , wherein:
each of the leader memory controller and the follower memory controller have a respective page table;
the follower memory controller arbitrates between memory access requests and refresh requests;
the follower memory controller selectively provides an updated page status to the leader memory controller; and
the leader memory controller updates its respective page table in response to the updated page status.
12. The electronic device of claim 1 , wherein:
the processor is operable to program a respective scheduling policy of at least one of the leader memory controller and the follower memory controller.
13. An electronic device comprising a semiconductor die having a first major surface and a second major surface, the semiconductor die comprising:
a processor region having a first side and a second side and comprising a leader memory controller;
a controller region having a first surface forming part of the first major surface, a second surface forming part of the second major surface, a first side adjacent to the second side of the processor region, and a second side, wherein the controller region comprises a follower memory controller that is electrically coupled to the leader memory controller; and
a memory region having a first surface forming part of the first major surface, a second surface forming part of the second major surface, a first side adjacent to the second side of the controller region, and a second side, wherein the memory region is electrically coupled to the controller region.
14. The electronic device of claim 13 , wherein the memory region comprises one of: a ferro-electric random access memory (FeRAM), a spin-torque transfer memory, a magneto-resistive memory, and a phase-change memory.
15. The electronic device of claim 13 , wherein:
the leader memory controller and the follower memory controller together issue commands received by the leader memory controller to the memory region in an order different from an order provided by the processor region based on a plurality of predetermined criteria.
16. The electronic device of claim 15 , wherein the leader memory controller comprises:
a command queue for storing memory access requests;
a page table for storing current page states of memory pages in the memory region; and
a picker for selecting entries from the command queue based on the plurality of predetermined criteria and providing selected entries with a corresponding page state from the page table to the follower memory controller.
17. A method for operating an electronic device, comprising:
processing data and generating memory access requests in response thereto;
scheduling an order of the memory access requests using a leader memory controller;
providing a sequence of the memory access requests in the order to a follower memory controller; and
issuing the sequence of memory access requests to a memory by the follower memory controller.
18. The method of claim 17 , wherein scheduling the order of the memory access requests using the leader memory controller comprises:
storing the memory access requests in a command queue of the leader memory controller;
picking selected memory access requests from the command queue by the leader memory controller based on a plurality of predetermined criteria; and
issuing memory commands by the follower memory controller to the memory in response to the picking.
19. The method of claim 18 , wherein the method further comprises:
storing current page states of memory pages in the memory by the leader memory controller;
providing the current page states of corresponding memory pages picked by the leader memory controller to the follower memory controller; and
issuing the memory commands to the memory according to the current page states, the issuing comprising issuing row commands selectively in response to the current page state of a corresponding memory page provided by the leader memory controller.
20. The method of claim 17 , wherein issuing the memory access requests to the memory by the follower memory controller comprises:
issuing the memory access requests to the memory by the follower memory controller without changing the order.
21. The method of claim 17 , wherein issuing the memory access requests to the memory by the follower memory controller to the memory comprises:
selectively changing the order by the follower memory controller in response to refresh requirements of the memory.
22. The method of claim 21 , wherein issuing the memory access requests to the memory by the follower memory controller to the memory further comprises:
providing an updated page status to the leader memory controller if the follower memory controller selectively changes the order; and
updating a respective page table of the leader memory controller in response to the updated page status.
23. The method of claim 17 , wherein the method further comprises:
processing data and generating memory access requests in response thereto in response to an application program; and
wherein the method further comprises selectively programming a respective scheduling policy of at least one of the leader memory controller and the follower memory controller in response to the application program.