Semiconductor device and method of building a pooled memory without using switches
A semiconductor device includes a first processor configured to generate a first memory physical address and a first memory request; a second processor configured to generate a second memory physical address and a second memory request; a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address; a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip. The first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.
1. A semiconductor device comprising:
a first processor configured to generate a first memory physical address and a first memory request;
a second processor configured to generate a second memory physical address and a second memory request;
a first system-on-chip physically connected to the first processor and configured to convert the first memory physical address into a first device address;
a second system-on-chip physically connected to the second processor and the first system-on-chip and configured to convert the second memory physical address into a second device address; and
a first memory and a second memory respectively and physically connected to the first system-on-chip and the second system-on-chip,
wherein the first system-on-chip and the second system-on-chip respectively forward the first memory request and the second memory request to one of a plurality of memories including the first memory and the second memory according to the first device address and the second device address.
2. The semiconductor device of claim 1 , wherein the first system-on-chip includes:
a first memory management unit (MMU) configured to convert the first memory physical address into the first device address; and
a router configured to determine whether the first device address corresponds to the first memory and configured to forward the first memory request to one of the first memory and the second system-on-chip.
3. The semiconductor device of claim 2 , wherein
the first system-on-chip and the second system-on-chip control the plurality of memories according to a compute express link (CXL) protocol.
4. The semiconductor device of claim 2 , wherein
the first memory has a device address in a first range,
the second memory has a device address in a second range that is greater than the first range, and
the router compares the first device address with the first range and forwards the first memory request.
5. The semiconductor device of claim 4 , wherein
the first range is defined from a start address to an end address, and
the router forwards the first memory request to the second system-on-chip when the first device address is greater than the end address.
6. The semiconductor device of claim 2 , further comprising:
a third processor configured to generate a third memory physical address and a third memory request; and
a third system-on-chip physically connected to the third processor, the first system-on-chip, and the second system-on-chip and configured to convert the third memory physical address into a third device address.
7. The semiconductor device of claim 6 , wherein
the router forwards the first memory request to an optimal path on which contour numbers are defied in order of proximity to a current system-on-chip.
8. The semiconductor device of claim 1 , wherein
the first and second system-on-chip connect through die-to-die interfaces or chip-to-chip interfaces.
9. A method of forwarding a memory request of a semiconductor device, the method comprising:
receiving, by a first processor, a first memory request and a first physical address to which the first memory request has to be forwarded;
converting the first physical address into a first device address by a first system-on-chip physically connected to the first processor;
comparing, by the first system-on-chip, the first device address with a device address of a first memory connected to the first system-on-chip;
forwarding the first memory request to the first memory when the first system-on-chip corresponds to the device address of the first memory;
forwarding the first memory request to a second system-on-chip connected to the first system-on-chip when the first system-on-chip does not correspond to the device address of the first memory;
comparing, by the second system-on-chip, the first device address with a device address of a second memory connected to the second system-on-chip;
forwarding the first memory request to the second memory when the second system-on-chip corresponds to the device address of the second memory; and
forwarding the first memory request to a third system-on-chip connected to the second system-on-chip when the second system-on-chip does not correspond to the device address of the second memory.
10. The method of claim 9 , wherein
the device address of the first memory is defined as a first range, and
the comparing of the first device address with the device address of the first memory includes comparing a smallest value of the first range with the first device address, and comparing a greatest value of the first range with the first device address.
11. The method of claim 9 , wherein
a path between the first system-on-chip and the third system-on-chip is an optimal path.