Three-dimensional flash memory for improving integration and operation method thereof
Disclosed are a three-dimensional flash memory, to which a GSL-removed structure is applied, and an operating method thereof. According to an embodiment, the three-dimensional flash memory comprises: a plurality of word lines which are formed extending in a horizontal direction on a substrate and are sequentially stacked; and a plurality of strings passing through the plurality of word lines and formed extending in one direction on the substrate, wherein each of the plurality of strings comprises a channel layer formed extending in the one direction and a charge storage layer formed extending in the one direction to surround the channel layer, and the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, and the channel layer comprises a back gate formed extending in the one direction while at least a part thereof is surrounded by the channel layer and an insulation film formed extending in the one direction between the back gate and the channel layer, and each of the plurality of strings includes the back gate. Accordingly, the three-dimensional flash memory has a GSL-removed structure.
1. A three-dimensional flash memory comprising:
a plurality of word lines which are formed by extending in a horizontal direction on a substrate and are sequentially stacked; and
a plurality of strings passing through the plurality of word lines and formed by extending in one direction on the substrate, wherein each of the plurality of strings comprises a channel layer formed by extending in the one direction and a charge storage layer formed by extending in the one direction to surround the channel layer, and the channel layer and the charge storage layer constitute a plurality of memory cells corresponding to the plurality of word lines, and the channel layer comprises a back gate formed by extending in the one direction while at least a part thereof is surrounded by the channel layer and an insulation film formed by extending in the one direction between the back gate and the channel layer,
wherein the three-dimensional flash memory has a structure in which aground selection line (GSL) is removed as each of the plurality of strings includes the back gate.
2. The three-dimensional flash memory of claim 1 , wherein a word line located at a lowermost end among the plurality of word lines forms a part of a dummy word line or memory cell word lines.
3. The three-dimensional flash memory of claim 2 , wherein the word line located at the lowermost end among the plurality of word lines is in an ON state at all times during memory operation when being used as the dummy word line.
4. The three-dimensional flash memory of claim 2 , wherein the word line located at the lowermost end among the plurality of word lines is supplied with a program voltage for a program operation when the word line is a word line of a target memory cell that is a target of the program operation during the program operation of the 3D flash memory, is floated when the word line is not the word line of the target memory cell subject to the program operation during the program operation, is supplied with a Gate-Induced Drain Leakage (GIDL) voltage for causing a GIDL phenomenon during an erase operation of the 3D flash memory, is supplied with a read voltage for a read operation when the word line is a word line of a target memory cell subject to the read operation and is supplied with a pass voltage when the word line is not the word line of the target memory cell subject to the read operation.
5. The three-dimensional flash memory of claim 2 , wherein, in the word line located at the lowermost end among the plurality of word lines, a hole supply film for supplying holes in an erase operation is disposed.
6. The three-dimensional flash memory of claim 5 , wherein, in an area corresponding to at least one String Selection Line (SSL) located above the plurality of word lines in each of the plurality of strings, the hole supply film for supplying the holes in the erase operation is disposed.
7. The three-dimensional flash memory of claim 2 , wherein the word line located at the lowermost end among the plurality of word lines is spaced apart from remaining word lines by a distance greater than a distance between the remaining word lines except for the word line located at the lowermost end among the plurality of word lines.
8. An erase operation method of a three-dimensional flash memory having a structure in which a Ground Selection Line (GSL) is removed by including a plurality of word lines which are formed by extending in a horizontal direction on a substrate and are sequentially stacked and a plurality of strings passing through the plurality of word lines and formed by extending in one direction on the substrate, each of the plurality of strings including a channel layer formed by extending in the one direction and a charge storage layer formed by extending in the one direction to surround the channel layer, and the channel layer and the charge storage layer constituting a plurality of memory cells corresponding to the plurality of word lines, and the channel layer including a back gate formed by extending in the one direction while at least a part thereof is surrounded by the channel layer and an insulation film formed by extending in the one direction between the back gate and the channel layer, the erase operation method comprising:
grounding remaining word lines except for a word line located at a lowermost end among the plurality of word lines; and
performing an erase operation on the plurality of strings by applying a Gate-Induced Drain Leakage (GIDL) voltage for causing GIDL phenomenon to the word line located at the lowermost end, at least one String Selection Line (SSL) located above the plurality of word lines, bit lines of a plurality of strings, and a common source line (CSL).