Stress-reduced silicon photonics semiconductor wafer
A stress-reduced silicon photonics semiconductor wafer includes a silicon nitride layer on a backside of the wafer. At least one silicon nitride stress-reduction configuration is on a topside of the wafer. At least one silicon nitride photonics device is also on the topside of the wafer. A silicon photonics device can be situated in the wafer.
1. A stress-reduced silicon photonics semiconductor wafer comprising:
a silicon nitride layer on a backside of said wafer;
at least one silicon nitride stress-reduction configuration on a topside of said wafer and occupying only a portion of said topside;
at least one silicon nitride photonics device on said topside of said wafer.
2. The semiconductor wafer of claim 1 , wherein said silicon photonics semiconductor wafer is a silicon-on-insulator (SOI) wafer having a top silicon layer, and wherein said at least one silicon nitride stress-reduction configuration is situated over said top silicon layer.
3. The semiconductor wafer of claim 1 , wherein said at least one silicon nitride stress-reduction configuration does not occupy areas corresponding to said at least one silicon nitride photonics device.
4. The semiconductor wafer of claim 1 , wherein said at least one silicon nitride stress-reduction configuration occupies more than half of a surface area of said topside of said wafer.
5. The semiconductor wafer of claim 1 , wherein said at least one silicon nitride stress-reduction configuration comprises a pattern of rectangular-shaped or square-shaped silicon nitride regions on said topside of said wafer.
6. The semiconductor wafer of claim 1 , wherein said at least one silicon nitride stress-reduction configuration is situated at least partially in a scribe line of said wafer.
7. The semiconductor wafer of claim 1 , wherein said at least one silicon nitride stress-reduction configuration is situated at least partially in a die of said wafer.
8. The semiconductor wafer of claim 1 , wherein said at least one silicon nitride photonics device is selected from the group consisting of a silicon nitride waveguide, and a silicon nitride resonator.
9. A method for making a stress-reduced silicon photonics semiconductor wafer, said method comprising:
forming a silicon nitride layer on a backside of said wafer;
forming at least one silicon nitride stress-reduction configuration on a topside of said wafer and occupying only a portion of said topside;
forming at least one silicon nitride photonics device on said topside of said wafer.
10. The method of claim 9 , wherein said forming said at least one silicon nitride stress-reduction configuration is performed concurrently with said forming said at least one silicon nitride photonics device.
11. The method of claim 9 , wherein said silicon photonics semiconductor wafer is a silicon-on-insulator (SOI) wafer having a top silicon layer, and wherein said at least one silicon nitride stress-reduction configuration is situated over said top silicon layer.
12. The method of claim 9 , wherein said at least one silicon nitride stress-reduction configuration does not occupy areas corresponding to said at least one silicon nitride photonics device.
13. The method of claim 9 , wherein said at least one silicon nitride stress-reduction configuration occupies more than half of a surface area of said topside of said wafer.
14. The method of claim 9 , wherein said at least one silicon nitride stress-reduction configuration comprises a pattern of rectangular-shaped or square-shaped silicon nitride regions on said topside of said wafer.
15. The method of claim 9 , wherein said at least one silicon nitride stress-reduction configuration is situated at least partially in a scribe line of said wafer.
16. A stress-reduced silicon photonics semiconductor die comprising:
a silicon nitride layer on a backside of said die;
a silicon nitride stress-reduction configuration on a topside of said die and occupying only a portion of said topside;
a silicon nitride photonics device on said topside of said die;
a silicon photonics device in said die.
17. The semiconductor die of claim 16 , wherein said silicon photonics semiconductor die is a silicon-on-insulator (SOI) die having a top silicon layer, and wherein said at least one silicon nitride stress-reduction configuration is situated over said top silicon layer.
18. The semiconductor die of claim 16 , wherein said silicon nitride stress-reduction configuration does not occupy areas corresponding to said silicon nitride photonics device.
19. The semiconductor die of claim 16 , wherein said at least one silicon nitride stress-reduction configuration comprises a pattern of rectangular-shaped or square-shaped silicon nitride regions on said topside of said die.
20. The semiconductor die of claim 16 , wherein said at least one silicon nitride photonics device is selected from the group consisting of a silicon nitride waveguide, and a silicon nitride resonator.