Bonded semiconductor devices having processor and static random-access memory and methods for forming the same
In an example, a semiconductor device includes a first semiconductor structure including a device layer, a first interconnect layer, and a first bonding layer. The device layer includes a processor and a logic circuit, and the first bonding layer includes a first bonding contact. The semiconductor device also includes a second semiconductor structure including an array of static random-access memory (SRAM) cells, a second interconnect layer, and a second bonding layer including a second bonding contact. The first bonding contact is in contact with the second bonding contact. The processor is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer. The logic circuit is electrically connected to the array of SRAM cells through the first interconnect layer, the first bonding contact, the second bonding contact, and the second interconnect layer.
1. A semiconductor device, comprising:
a first semiconductor structure comprising a device layer, a first interconnect layer, and a first bonding layer, wherein the device layer comprises a processor and a first logic circuit, and the first bonding layer comprises a plurality of first bonding contacts wherein the plurality of first bonding contacts are arranged in a first bonding contact pattern; and
a second semiconductor structure comprising a plurality of static random-access memory (SRAM) arrays, each SRAM array having a plurality of SRAM cells, each SRAM array disposed so as to be laterally spaced apart from all other SRAM arrays of the plurality of SRAM arrays, a second logic circuit, a second interconnect layer, and a second bonding layer comprising a plurality of second bonding contacts wherein the plurality of second bonding contacts are arranged in a second bonding contact pattern,
wherein the first semiconductor structure and the second semiconductor structure are bonded together in a face-to-face orientation such that the plurality of first bonding contacts arranged in the first bonding contact pattern, and the plurality of second bonding contacts arranged in the second bonding contact pattern are in physical contact with each other respectively,
wherein the second logic circuit is electrically connected to one or more SRAM arrays of the plurality of SRAM arrays,
wherein a first SRAM array and a second SRAM array are laterally spaced apart from each other in both a first direction and a second direction that is different from the first direction.
2. The semiconductor device of claim 1 , wherein the first logic circuit comprises an interface circuit, and the second logic circuit comprises a peripheral circuit.
3. The semiconductor device of claim 2 , wherein the interface circuit comprises at least one of an input/output (I/O) circuit or a bus circuit.
4. The semiconductor device of claim 2 , wherein the peripheral circuit comprises at least one of a row decoder, a column decoder, or a sense amplifier.
5. The semiconductor device of claim 1 , wherein the first logic circuit comprises a peripheral circuit, and the second logic circuit comprises an interface circuit.
6. The semiconductor device of claim 2 , wherein the peripheral circuit is coupled to at least one SRAM array of the plurality of SRAM arrays.
7. The semiconductor device of claim 5 , wherein the peripheral circuit is coupled to at least one SRAM array of the plurality of SRAM arrays.
8. The semiconductor device of claim 5 , wherein the peripheral circuit comprises at least one of a row decoder, a column decoder, and a sense amplifier, and wherein the interface circuit comprises at least one of an I/O circuit and a bus circuit.
9. The semiconductor device of claim 1 , wherein the processor comprises at least one of a central processing unit, a graphics processing unit, a digital signal processor, a tensor processing unit, a vision processing unit, a neural processing unit, a synergistic processing unit, a physics processing unit, and an image processing unit.
10. The semiconductor device of claim 9 , wherein the processor comprises one or more cores, each of which is configured to read and execute instructions.
11. The semiconductor device of claim 10 , wherein the processor comprises complementary metal oxide semiconductor (CMOS) circuits.
12. A semiconductor device, comprising:
a first semiconductor structure comprising a first substrate having a first side and a second side, a first interconnect layer, a first logic circuit disposed on the first side of the first substrate, a first bonding layer, a processor disposed on the first side of the first substrate, wherein the first bonding layer comprises a plurality of first bonding contacts; and
a second semiconductor structure comprising a second substrate having a first side and a second side, a plurality of memory arrays disposed on the first side of the second substrate, each memory array having a plurality of memory cells, each memory array disposed so as to be laterally spaced apart from all other memory arrays of the plurality of memory arrays and such that no memory array of the plurality of memory arrays abuts any other memory array of the plurality of memory arrays, a second interconnect layer, a second logic circuit disposed on the first side of the second substrate, and a second bonding layer comprising a plurality of second bonding contacts,
wherein the plurality of memory arrays are disposed such that no second bonding contacts are overlying any of the plurality of memory arrays,
wherein the first semiconductor structure and the second semiconductor structure are bonded together in a face-to-face orientation such that a first one of the plurality of first bonding contacts is in physical contact with a first one of the plurality of second bonding contacts,
wherein the second logic circuit is electrically connected to one or more memory arrays of the plurality of memory arrays.
13. The semiconductor device of claim 12 , wherein each memory array of the plurality of memory arrays is a static random-access memory (SRAM) array.
14. The semiconductor device of claim 13 , wherein the first logic circuit is coupled to at least one of the plurality of memory arrays.
15. The semiconductor device of claim 14 , wherein at least one of the memory arrays is a cache region.
16. The semiconductor device of claim 15 , wherein the processor is coupled to at least one of the plurality of memory arrays through the first interconnect layer, the first bonding layer, the second bonding layer and the second interconnect layer.
17. The semiconductor device of claim 12 , wherein the processor comprises a plurality of cores.
18. The semiconductor device of claim 12 , wherein the first semiconductor structure comprises a pad-out layer disposed on the second side of the first substrate.
19. The semiconductor device of claim 12 , wherein the second semiconductor structure comprises a pad-out layer disposed on the second side of the second substrate.
20. The semiconductor device of claim 12 , wherein the processor comprises at least one of a central processing unit, a graphics processing unit, a digital signal processor, a tensor processing unit, a vision processing unit, a neural processing unit, a synergistic processing unit, a physics processing unit, and an image processing unit, wherein the processor comprises one or more cores, each of which is configured to read and execute instructions, and wherein the processor comprises complementary metal oxide semiconductor (CMOS) circuits.