Electrostatic discharge circuit
An ESD circuit includes a first P-type transistor, a second P-type transistor, a third P-type transistor, a first ESD current path, a second ESD current path, a biasing circuit and a control circuit. The control circuit is connected between the pad and a first node. The first P-type transistor is connected with the pad, the control circuit and a second node. The first ESD current path is connected between the second node and the first node. The second ESD current path is connected between the second node and the first node. The second P-type transistor is connected with the pad, the control circuit and a third node. The biasing circuit is connected between the third node and the first node. The third P-type transistor is connected with the pad, the third node, and a fourth node. The internal circuit is connected between the fourth node and the first node.
1. An electrostatic discharge (ESD) circuit connected with a pad and an internal circuit, the ESD circuit comprising:
a control circuit, wherein the control circuit is connected between the pad and a first node;
a first P-type transistor, wherein a first source/drain terminal of the first P-type transistor is connected with the pad, a gate terminal of the first P-type transistor is connected with the control circuit, and a second source/drain terminal of the first P-type transistor is connected with a second node;
a first ESD current path, wherein the first ESD current path is connected between the second node and the first node;
a second ESD current path, wherein the second ESD current path is connected between the second node and the first node;
a second P-type transistor, wherein a first source/drain terminal of the second P-type transistor is connected with the pad, a gate terminal of the second P-type transistor is connected with the control circuit, and a second source/drain terminal of the second P-type transistor is connected with a third node;
a biasing circuit, wherein the biasing circuit is connected between the third node and the first node; and
a third P-type transistor, wherein a first source/drain terminal of the third P-type transistor is connected with the pad, a gate terminal of the third P-type transistor is connected with the third node, and a second source/drain terminal of the third P-type transistor is connected with a fourth node;
wherein the internal circuit is connected between the fourth node and the first node;
wherein in a normal working state, the first P-type transistor and the second P-type transistor are turned off, the third P-type transistor is turned on, and a first supply voltage received by the pad is transmitted to the fourth node and the internal circuit through the third P-type transistor;
wherein when the pad receives a positive ESD zap, the control circuit provides a control voltage to turn on the first P-type transistor and the second P-type transistor, the third P-type transistor is turned off to isolate the internal circuit from the pad, and an ESD current flows from the pad to the first node through the first source/drain terminal of the first P-type transistor, a channel region of the first P-type transistor, the second source/drain terminal of the first P-type transistor and the first ESD current path.
2. The ESD circuit as claimed in claim 1 , wherein the control circuit comprises:
a first resistor, wherein a first terminal of the first resistor is connected with the pad, and a second terminal of the first resistor is connected with a fifth node; and
a first capacitor, wherein a first terminal of the first capacitor is connected with the fifth node, and a second terminal of the first capacitor is connected with the first node;
wherein the gate terminal of the first P-type transistor is connected with the fifth node, and the gate terminal of the second P-type transistor is connected with the fifth node.
3. The ESD circuit as claimed in claim 2 , wherein in the normal working state of the ESD circuit, the first capacitor is charged to pull up a voltage at the fifth node a to provide a control voltage to turn off the first P-type transistor and the second P-type transistor.
4. The ESD circuit as claimed in claim 2 , wherein when the pad receives a positive ESD zap, the first capacitor acts as a short circuit to pull down a voltage at the fifth node to turn on the first P-type transistor and the second P-type transistor.
5. The ESD circuit as claimed in claim 4 , wherein during a turn-on period of the first P-type transistor and the second P-type transistor, the first capacitor is charged according to a voltage at the pad to pull up the voltage at the fifth node and an ESD current flows from the pad to the first node through the first source/drain terminal of the first P-type transistor, a channel region of the first P-type transistor M 1 , the second source/drain terminal of the first P-type transistor M 1 and the first ESD current path.
6. The ESD circuit as claimed in claim 5 , wherein at the end of the turn-on period, the first capacitor is charged to a voltage level to turn off the first P-type transistor and the second P-type transistor.
7. The ESD circuit as claimed in claim 2 , wherein the biasing circuit includes:
a second resistor, wherein a first terminal of the second resistor is connected with the third node, and a second terminal of the first resistor is connected with a sixth node; and
z diodes, wherein an anode terminal of the first diode of the z diodes in the biasing circuit is connected with the sixth node, the cathode terminal of the last diode of the z diodes in the biasing circuit is connected with the first node, the anode terminal of any of the other diodes in the biasing circuit is connected with the cathode terminal of the previous diode, the cathode of any of the other diodes in the biasing circuit is connected with the anode terminal of the next diode, and z is the integer.
8. The ESD circuit as claimed in claim 7 , wherein in the normal working state, the pad receives the first supply voltage and the first node receives a second supply voltage, and the biasing circuit provides a bias voltage lower than the first supply voltage to the third node to turn on the third P-type transistor.
9. The ESD circuit as claimed in claim 7 , wherein a first resistance of the first resistor is larger than a second resistance of the second resistor.
10. The ESD circuit as claimed in claim 1 , wherein the first ESD current path includes x diodes, an anode terminal of the first diode of the x diodes in the first ESD current path is connected with the second node, a cathode terminal of the last diode of the x diodes in the first ESD current path is connected with the first node, the anode terminal of any of the other diodes in the first ESD current path is connected with the cathode terminal of the previous diode, the cathode of any of the other diodes in the first ESD current path is connected with the anode terminal of the next diode, and x is an integer.
11. The ESD circuit as claimed in claim 10 , wherein the second ESD current path includes y diodes, the anode terminal of the first diode of the y diodes in the second ESD current path is connected with the first node, the cathode terminal of the last diode of the y diodes in the second ESD current path is connected with the second node, the anode terminal of any of the other diodes in the second ESD current path is connected with the cathode terminal of the previous diode, the cathode of any of the other diodes in the second ESD current path is connected with the anode terminal of the next diode, y is the integer, and x is greater than y.
12. The ESD circuit as claimed in claim 10 , wherein the second ESD current path includes a diode, the anode terminal of the diode in the second ESD current path is connected with the first node, and the cathode terminal of the diode in the second ESD current path is connected with the second node.
13. The ESD circuit as claimed in claim 1 , wherein when the pad receives a negative ESD zap, an ESD current flows from the first node to the pad through the second ESD current path, the second source/drain terminal of the first P-type transistor, a parasitic diode of the first P-type transistor and the first source/drain terminal of the first P-type transistor.