Resistive memory element arrays with shared electrode strips
Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes. The structure further comprises a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes. The first top electrode is shared by the first plurality of resistive memory elements, and the second top electrode is shared by the second plurality of resistive memory elements.
1. A structure comprising:
a semiconductor substrate;
a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes, the first top electrode shared by the first plurality of resistive memory elements;
a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes, the second top electrode shared by the second plurality of resistive memory elements;
a plurality of field-effect transistors, each of the plurality of field-effect transistors including a drain region that is respectively connected to one of the first plurality of bottom electrodes;
a dielectric layer positioned between the plurality of field-effect transistors and the semiconductor substrate;
a first well in the semiconductor substrate; and
a plurality of deep trench isolation regions penetrating fully through the dielectric layer and fully through the first well to divide the first well into a plurality of isolated sections, each isolated section of the first well positioned beneath one of the plurality of field-effect transistors.
2. The structure of claim 1 wherein the first top electrode is surrounded by a first perimeter, and further comprising:
a first metal feature connected to the first top electrode with a first overlapping arrangement, the first metal feature fully enclosed within the first perimeter of the first top electrode.
3. The structure of claim 2 wherein the first top electrode is positioned in a vertical direction between the first metal feature and the first switching layer.
4. The structure of claim 2 wherein the first metal feature directly contacts the first top electrode to form a via-less connection.
5. The structure of claim 4 wherein the first metal feature is connected to the first top electrode without an intervening via.
6. The structure of claim 2 wherein the second top electrode is surrounded by a second perimeter, and further comprising:
a second metal feature connected to the second top electrode with a second overlapping arrangement, the second metal feature fully enclosed within the second perimeter of the second top electrode.
7. The structure of claim 6 wherein the first top electrode is positioned in a vertical direction between the first metal feature and the first switching layer, and the second top electrode is positioned in the vertical direction between the second metal feature and the second switching layer.
8. The structure of claim 6 wherein the first metal feature directly contacts the first top electrode, and the second metal feature directly contacts the second top electrode.
9. The structure of claim 1 wherein the first well has a first conductivity type, and further comprising:
a second well in the semiconductor substrate, the second well having a second conductivity type opposite to the first conductivity type,
wherein the plurality of deep trench isolation regions penetrate into the second well.
10. The structure of claim 1 further comprising:
a plurality of shallow trench isolation regions penetrating fully through the dielectric layer.
11. The structure of claim 1 wherein the plurality of isolated sections of the first well are configured to be independently biased.
12. The structure of claim 1 further comprising:
a bit line longitudinally aligned parallel to the first top electrode and the second top electrode,
wherein each of the plurality of field-effect transistors includes a source region that is respectively connected to the bit line.
13. The structure of claim 12 wherein the plurality of field-effect transistors include a shared gate electrode defining a word line, and the word line is longitudinally aligned transverse to the bit line.
14. The structure of claim 1 wherein the first plurality of bottom electrodes are arranged in a first row, and the first top electrode is longitudinally aligned parallel to the first row.
15. The structure of claim 14 wherein the second plurality of bottom electrodes are arranged in a second row, and the second top electrode is longitudinally aligned parallel to the second row.
16. The structure of claim 1 wherein the first top electrode and the second top electrode are separated by a gap.
17. The structure of claim 1 wherein the first top electrode is surrounded by a perimeter, and further comprising:
a first metal feature connected to the first top electrode with a first overlapping arrangement, the first metal feature having a perimeter positioned inside the perimeter of the first top electrode.
18. The structure of claim 1 wherein each of the first plurality of resistive memory elements includes one of the first plurality of bottom electrodes, and each of the second plurality of resistive memory elements includes one of the second plurality of bottom electrodes.
19. A method comprising:
forming a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes, wherein the first top electrode are shared by the first plurality of resistive memory elements;
forming a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes, wherein the second top electrode is shared by the second plurality of resistive memory elements;
forming a plurality of field-effect transistors, wherein each of the plurality of field-effect transistors including a drain region that is respectively connected to one of the first plurality of bottom electrodes, and a dielectric layer is positioned between the plurality of field-effect transistors and a semiconductor substrate;
forming a well in the semiconductor substrate; and
forming a plurality of deep trench isolation regions penetrating fully through the dielectric layer and fully through the well to divide the well into a plurality of isolated sections, wherein each isolated section of the well is positioned beneath one of the plurality of field-effect transistors.
20. The method of claim 19 wherein the first top electrode is surrounded by a first perimeter, and further comprising:
forming a metal feature connected to the first top electrode with an overlapping arrangement,
wherein the metal feature is enclosed within the first perimeter of the first top electrode.