Imaging device with embedded conductive layers
View Patent ↗The present invention relates to a highly functional imaging device that can be manufactured through a small number of steps. A first stacked body is formed in which a circuit provided with a transistor including a metal oxide in its channel formation region (hereinafter, OS transistor) is stacked over a circuit including a Si transistor. A second stacked body is formed in which an OS transistor is provided over a Si photodiode. Layers including the OS transistors of the first stacked body and the second stacked body are bonded to each other to obtain electrical connection between circuits. With such a structure, even when a structure is employed in which a plurality of circuits having different functions are stacked, the number of polishing steps and bonding steps can be reduced, improving the yield.
1. An imaging device comprising:
a first circuit comprising a reading circuit, the reading circuit comprising a first transistor comprising silicon in a channel formation region;
a first insulating layer over the first circuit;
a second circuit comprising a plurality of memory cells arranged in a matrix over the first insulating layer, each of the plurality of memory cells comprising a second transistor comprising a first metal oxide in a channel formation region;
a second insulating layer over the second circuit;
a third insulating layer over and in direct contact with the second insulating layer;
a first conductive layer comprising a region embedded in the second insulating layer and the third insulating layer;
a fourth insulating layer over and in direct contact with the third insulating layer;
a fifth insulating layer over and in direct contact with the fourth insulating layer;
a second conductive layer comprising a region embedded in the fourth insulating layer and the fifth insulating layer;
a third circuit comprising a part of a pixel circuit over the fifth insulating layer, the part of the pixel circuit comprising a third transistor comprising a second metal oxide in a channel formation region;
a sixth insulating layer over the third circuit; and
a photoelectric conversion device over the sixth insulating layer,
wherein the photoelectric conversion device is electrically connected to the part of the pixel circuit,
wherein the pixel circuit is electrically connected to the second conductive layer,
wherein the second conductive layer is in direct contact with the first conductive layer,
wherein the first conductive layer is electrically connected to the reading circuit,
wherein the reading circuit is electrically connected to the plurality of memory cells, and
wherein the reading circuit is configured to read out analog data from the pixel circuit, convert the analog data into digital data, and output the digital data to the plurality of memory cells.
2. The imaging device according to claim 1 ,
wherein the photoelectric conversion device is a photodiode comprising silicon in a photoelectric conversion layer.
3. The imaging device according to claim 1 ,
wherein each of the first metal oxide and the second metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).
4. The imaging device according to claim 1 ,
wherein the first conductive layer and the second conductive layer comprise a same metal material, and
wherein the third insulating layer and the fourth insulating layer comprise a same insulating material.
5. The imaging device according to claim 1 ,
wherein the reading circuit further comprises a first capacitor over the first transistor and under the first insulating layer, and
wherein each of the plurality of memory cells further comprises a second capacitor over the second transistor and under the second insulating layer.
6. The imaging device according to claim 1 , further comprising a light-blocking layer,
wherein the light-blocking layer is provided between the photoelectric conversion device and the third circuit.
7. The imaging device according to claim 1 , further comprising:
a row driver and a column driver each configured to drive the plurality of memory cells,
wherein the fourth circuit row driver and the column driver are provided on a same substrate as the reading circuit, and
wherein the row driver comprises a transistor comprising silicon in a channel formation region.
8. The imaging device according to claim 1 ,
wherein the pixel circuit comprises the photoelectric conversion device, the third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and a third capacitor,
wherein one of a source and a drain of the sixth transistor is electrically connected to one electrode of the photoelectric conversion device,
wherein the other of the source and the drain of the sixth transistor is electrically connected to one of a source and a drain of the seventh transistor and one of a source and a drain of the third transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a gate of the fourth transistor and one electrode of the third capacitor, and
wherein one of a source and a drain of the fourth transistor is electrically connected to one of a source and a drain of the fifth transistor.
9. The imaging device according to claim 8 ,
wherein at least one of the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor comprises silicon in a channel formation region.
10. The imaging device according to claim 1 ,
wherein each of the first metal oxide and the second metal oxide comprises at least In.
11. An electronic device comprising:
the imaging device according to claim 1 ; and
a display portion,
wherein the display portion is capable of displaying an image taken with the imaging device.
12. An imaging device comprising:
a first layer comprising a reading circuit, the reading circuit comprising a first transistor comprising silicon in a channel formation region;
a second layer on the first layer, the second layer comprising:
a plurality of memory cells arranged in a matrix, each of the plurality of memory cells comprising a second transistor comprising a first metal oxide in a channel formation region;
a first insulating layer over the plurality of memory cells; and
a first conductive layer comprising a region embedded in the first insulating layer;
a third layer on the second layer, the third layer comprising:
a second insulating layer over and in direct contact with the first insulating layer;
a second conductive layer comprising a region embedded in the second insulating layer and being in direct contact with the region of the first conductive layer; and
a part of a pixel circuit over the second conductive layer, the part of the pixel circuit comprising a third transistor comprising a second metal oxide in a channel formation region; and
a fourth layer on the third layer, the fourth layer comprising a photoelectric conversion device included in the pixel circuit,
wherein the photoelectric conversion device is electrically connected to the third transistor,
wherein the pixel circuit in the third layer is electrically connected to the reading circuit in the first layer via the second conductive layer and the first conductive layer,
wherein the reading circuit in the first layer is electrically connected to the plurality of memory cells in the second layer, and
wherein the reading circuit is configured to read out analog data from the pixel circuit, convert the analog data into digital data, and output the digital data to the plurality of memory cells.
13. The imaging device according to claim 12 ,
wherein the photoelectric conversion device is a photodiode comprising silicon in a photoelectric conversion layer.
14. The imaging device according to claim 12 ,
wherein each of the first metal oxide and the second metal oxide comprises In, Zn, and M (M is one or more of Al, Ti, Ga, Ge, Sn, Y, Zr, La, Ce, Nd, and Hf).
15. The imaging device according to claim 12 ,
wherein each of the first metal oxide and the second metal oxide comprises at least In.
16. The imaging device according to claim 12 ,
wherein the first conductive layer and the second conductive layer comprise a same metal material, and
wherein the first insulating layer and the second insulating layer comprise a same insulating material.
17. The imaging device according to claim 12 ,
wherein the reading circuit further comprises a first capacitor over the first transistor, and
wherein each of the plurality of memory cells further comprises a second capacitor over the second transistor and under the first insulating layer.
18. The imaging device according to claim 12 ,
wherein the first layer further comprises a column driver and a row driver for driving the plurality of memory cells, and
wherein the row driver comprises a transistor comprising silicon in a channel formation region.
19. The imaging device according to claim 12 ,
wherein the part of the pixel circuit comprises the third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a third capacitor.
20. An imaging device comprising:
a first layer comprising a reading circuit, a row driver, and a column driver, each of the reading circuit and the row driver comprising a first transistor comprising silicon in a channel formation region;
a second layer on the first layer, the second layer comprising:
a plurality of memory cells arranged in a matrix, each of the plurality of memory cells comprising a second transistor comprising a first metal oxide in a channel formation region;
a first insulating layer over the plurality of memory cells; and
a first conductive layer comprising a region embedded in the first insulating layer;
a third layer on the second layer, the third layer comprising:
a second insulating layer over and in direct contact with the first insulating layer;
a second conductive layer comprising a region embedded in the second insulating layer and being in direct contact with the region of the first conductive layer; and
a part of a pixel circuit over the second conductive layer, the part of the pixel circuit comprising a third transistor comprising a second metal oxide in a channel formation region; and
a fourth layer on the third layer, the fourth layer comprising a photoelectric conversion device included in the pixel circuit,
wherein each of the row driver and the column driver is configured to drive the plurality of memory cells,
wherein the photoelectric conversion device is electrically connected to the third transistor,
wherein the pixel circuit is electrically connected to the reading circuit via the second conductive layer and the first conductive layer, and
wherein the reading circuit is configured to read out analog data from the pixel circuit, convert the analog data into digital data, and output the digital data to the plurality of memory cells.