Granted Patent B2

US 12,379,412 · App. 18/296,598 · Granted Aug 5, 2025

Inventors: Joshua Todd (Tolland, CT); Gabriel Fletcher (Colchester, CT)

Assignee: HAMILTON SUNDSTRAND SPACE SYSTEMS INTERNATIONAL, INC.

G01R31/2872G01T1/026H03K19/0033

Abstract

Claims (64)

1. A system for detecting radiation events, comprising:

a test memory having memory blocks;

a controller having controller memory;

an integrated circuit (IC) array having IC chains, wherein each of the IC chains has a plurality of IC elements that is response to and generates a voltage when exposed to a radiation event;

a dosimeter configured to record an accumulated amount of radiation exposure to the system,

wherein the controller is configured to perform steps of:

initializing the test memory, the IC array and the dosimeter;

monitoring for an unexpected signal from an IC chain and for unexpected data in a memory block of the test memory; and

identifying the radiation event upon one or more of receiving the unexpected signal and identifying unexpected data in a memory block of the test memory.

2. The system of claim 1 , wherein each of the IC chains includes:

an input comparator;

an output comparator; and

a plurality of buffers connected in series between the input and output comparators.

3. The system of claim 1 , further comprising:

a substrate having first and second sides, and

wherein the IC chains are disposed on the first and second sides of the substrate.

4. The system of claim 3 , wherein:

the IC array include radiation hardened (rad-hard) IC chains and non-rad-hard IC chains that are positioned on the first and second sides of the substrate.

5. The system of claim 4 , wherein:

the rad-hard IC chains and the non-rad-hard IC chains alternate at least on a first side of the substrate.

6. The system of claim 5 , wherein:

the rad-hard IC chains and the non-rad-hard IC chains are configured in a first alternating pattern on the first side of the substrate and a second alternating pattern on the second side of the substrate, where the first and second alternating patterns are either opposite each other or are the same as each other.

7. The system of claim 1 , wherein upon identifying the radiation event, the controller is configured to perform steps of:

polling the dosimeter for a cumulative total radiation exposure to the system;

updating system counter data in the controller memory to a cumulative total observed radiation events; and

storing in the controller memory a data-record including a timestamp of the radiation event and the cumulative total radiation exposure to the system.

8. The system of claim 7 , wherein when monitoring for unexpected signals from the IC array, the controller is configured to perform steps of:

setting a watch dog timer (WDT) to wait for signal anomalies; and

monitoring for receipt of the unexpected signal from the IC array.

9. The system of claim 8 , wherein upon identifying the radiation event, the controller is configured to perform steps of:

testing an integrity of the IC array; and

upon verifying the integrity of the IC array, updating an IC array counter data in the controller memory corresponding to the IC chain exposed to the radiation event, otherwise deactivating the IC chain exposed to the radiation event, and not updating the IC array counter data.

10. The system of claim 9 , wherein when verifying the integrity of the IC array, the controller is configured to perform the steps of:

identifying the IC chain that transmitted the unexpected signal from being energized by the radiation event;

transmitting an input signal to the IC chain;

monitoring for an output signal from the IC chain; and

receiving the output signal from the IC chain, thereby verifying the IC chain.

11. The system of claim 10 , wherein the controller is configured to periodically perform the steps of:

setting the WDT to wait for signal anomalies;

at the end of a predetermined duration, transmitting the input signal to each of the IC chains in the IC array;

monitoring the IC array for the output signal from each of the IC chains, and

one of:

receiving the output signal from each of the IC chains, thereby verifying each the IC chains; and

not receiving the output signal from one or more of the IC chains, thereby failing to verify the one or more of the IC chains and verifying a reminder of the IC chains.

12. The system of claim 1 , wherein when monitoring for the unexpected data in the test memory, the controller is configured to perform steps of:

polling the test memory to obtain polled values, periodically or after receiving the unexpected signal from the IC array;

comparing the polled values with previously written values to identify differences, and

one of:

observing the unexpected data in the memory block by identifying a difference between the polled values and the previously written values, thereby identifying the radiation event; and

not observing the unexpected data by not identifying the difference between the polled values and the previously written values, thereby not identifying the radiation event.

13. The system of claim 12 , wherein upon identifying the radiation event, the controller is further configured to perform steps of:

testing an integrity of the test memory;

upon verifying the integrity of the test memory, updating memory array counter data in the controller memory corresponding to the memory block exposed to the radiation event, otherwise not updating the memory array counter data.

14. The system of claim 13 , wherein when verifying the integrity of the test memory, the controller is configured to perform steps of:

identifying the memory block that contains the unexpected data, thereby identifying the memory block that was exposed to the radiation event;

attempting to rewrite the memory block, and

one of:

determining that the memory block is capable of being rewritten, thereby verifying the integrity of the test memory; or

determining that the memory block is incapable of being rewritten, thereby failing to verify the integrity of the test memory.

15. The system of claim 1 , wherein the controller is configured to periodically perform steps of:

attempting to rewrite all of the memory blocks, and

one of:

determining that all of the memory blocks are capable of being rewritten, thereby verifying the integrity of the test memory; or

determining that one or more of the memory blocks is incapable of being rewritten, thereby failing to verify the integrity of one or more of the memory blocks of the test memory, and verifying a reminder of the memory blocks.

Assignments (1)

Continuity (1)

References Cited (12)