Granted Patent B2

US 12,379,810 · App. 18/635,805 · Granted Aug 5, 2025

Inventor: Sadao Yamamoto (Saitama, JP)

Assignee: Wacom Co., Ltd.

G06F3/0441G06F3/03545G06F3/038G06F3/0416G06F3/0442H04L1/0061

Abstract

Claims (30)

1. An integrated circuit for a pen, the integrated circuit comprising:

reception circuitry configured to receive an uplink signal generated according to a first protocol; and

transmission circuitry configured to transmit, according to the first protocol, a downlink signal based on a reception timing of the uplink signal and a command included in the uplink signal, wherein,

in a case where the reception circuitry receives the uplink signal that is in a normal state (uplink signal NUS) in a first period, the transmission circuitry transmits the downlink signal including data according to the command included in the uplink signal NUS, and

in a case where the reception circuitry receives the uplink signal that is in a special state (uplink signal SUS) in a second period subsequent to the first period, the transmission circuitry transmits the downlink signal including data according to the command included in the uplink signal NUS received in the first period.

2. The integrated circuit for a pen according to claim 1 , wherein the special state means that an abnormality is detected in decoding of the command included in the uplink signal SUS.

3. The integrated circuit for a pen according to claim 2 , wherein the abnormality is that a decoding result does not include a codeword.

4. The integrated circuit for a pen according to claim 2 , wherein

the uplink signal SUS includes an error detection code, and

the abnormality is that an error is detected based on the error detection code.

5. The integrated circuit for a pen according to claim 2 , wherein the abnormality is that a value of a first bit that is supposed to be a first value in the first protocol supported by the pen is a second value different from the first value.

6. The integrated circuit for a pen according to claim 5 , wherein, in a second protocol not supported by the pen, the value of the first bit is supposed to be the second value.

7. The integrated circuit for a pen according to claim 1 , wherein the transmission circuitry stops transmitting the downlink signal when the reception circuitry continues to receive the uplink signal SUS for a predetermined period.

8. The integrated circuit for a pen according to claim 1 , wherein a transmission timing of the downlink signal is determined based on the reception timing of the uplink signal SUS.

9. The integrated circuit for a pen according to claim 1 , wherein

the uplink signal NUS generated according to the first protocol supported by the pen includes a known synchronization signal, while the uplink signal SUS generated according to a second protocol not supported by the pen includes a synchronization signal which only partially matches the known synchronization signal, and

the special state means that the synchronization signal included in the uplink signal SUS matches only a part of the known synchronization signal and that an abnormality is detected in decoding of the command included in the uplink signal SUS.

10. The integrated circuit for a pen according to claim 9 , wherein the part of the known synchronization signal corresponds to a chip width of a spread code used for spreading the known synchronization signal, or corresponds to a code included in the spread code.

11. The integrated circuit for a pen according to claim 9 , wherein the part of the known synchronization signal is a top part of the known synchronization signal.

12. An integrated circuit for a pen, the integrated circuit comprising:

reception circuitry configured to receive both a first uplink signal generated according to a first protocol and a second uplink signal generated according to a second protocol different from the first protocol,

control circuitry configured to control operation of the pen in at least two operation modes, and

transmission circuitry configured to transmit a downlink signal, wherein,

in a case where the reception circuitry receives the second uplink signal, the control circuitry enters a second operation mode according to the second protocol, and

regardless of whether the reception circuitry operating in the second operation mode receives the first uplink signal according to the first protocol or the second uplink signal according to the second protocol, the transmission circuitry operating in the second operation mode transmits a second downlink signal according to the second protocol.

13. The integrated circuit for a pen according to claim 12 , wherein, when the reception circuitry operating in the second operation mode detects only the first uplink signal without detecting the second uplink signal for more than a predetermined period, the control circuitry shifts to a discovery mode for discovering a sensor controller.

14. The integrated circuit for a pen according to claim 12 , wherein, when the reception circuitry operating in a first operation mode according to the first protocol receives, through the first or second uplink signal, a command instructing entry into the second operation mode, the control circuitry shifts to the second operation mode.

15. The integrated circuit for a pen according to claim 12 , wherein

in a case where the reception circuitry receives the first uplink signal, the control circuitry enters a first operation mode according to the first protocol, and the transmission circuitry transmits a first downlink signal according to the first protocol, and

the first downlink signal includes flag information indicating whether the pen supports only the first protocol or supports both the first and second protocols.

Continuity (3)

References Cited (27)