Quantum circuit synthesis using CSP

1. A method comprising:

obtaining a functional-level representation of a quantum circuit, the functional-level representation comprises a first functional blocks and a second functional block, the first functional block defining a first operation of the quantum circuit over at least two cycles, the second functional block defining a second operation of the quantum circuit over at least two cycles, wherein the functional-level representation defines a relationship between the first functional block and the second functional block;

determining a Constraint Satisfaction Problem (CSP) based on the functional-level representation of the quantum circuit, wherein the CSP comprises one or more constraints based on the relationship between the first functional block and the second functional block;

automatically solving the CSP to obtain a solution to the CSP, wherein said automatically solving comprises:

identifying a first implementation to the first functional block that adheres to the one or more constraints; and

identifying a second implementation to the second functional block that adheres to the one or more constraints; and

synthesizing a gate-level representation of the quantum circuit using the first implementation and the second implementation.

2. The method of claim 1 , wherein said identifying the first implementation comprises selecting a first gate-level implementation of the functional block from a function library, wherein the function library comprises a pre-existing set of alternative implementations for the first functional block.

3. The method of claim 2 , wherein the first gate-level implementation of the first functional block comprises at least two gates and at least two qubits.

4. The method of claim 2 , wherein the function library defines a different valuation to a set of properties for each alternative gate-level implementation of the first functional block, wherein the first gate-level implementation is selected based on valuations of the set of properties that adhere to the one or more constraints.

5. The method of claim 4 , wherein the set of properties comprises:

a depth of the alternative gate-level implementation;

a number of qubits utilized by the alternative gate-level implementation; and

a number of auxiliary qubits utilized by the alternative gate-level implementation.

6. The method of claim 4 , wherein the set of properties comprises at least one of:

a precision error of the alternative implementation; and

a hardware error rate of the alternative implementation.

7. The method of claim 4 , wherein the set of properties comprises at least one of:

an entanglement caused by the alternative gate-level implementation; and

a number of auxiliary qubits released by the alternative gate-level implementation.

8. The method of claim 1 , wherein the gate-level representation comprises a set of qubits and a set of gates, wherein each gate of the set of gates defining operations on the set of qubits or portion thereof by the quantum circuit at a different cycle, wherein the gate-level representation is devoid of any block that defines a function over more than a single cycle or that is implemented using more than a single gate.

9. The method of claim 1 ,

wherein the CSP defines a global constraint on a number of qubits utilized by the quantum circuit at a same cycle; and

wherein the CSP defines a global constraint on a hardware error rate of the quantum circuit.

10. The method of claim 1 , wherein the CSP defines an objective function to be optimized, wherein the objective function is based on at least one of:

a depth of the quantum circuit, wherein the depth of the quantum circuit indicates a number of cycles of the quantum circuit;

an area of the quantum circuit, wherein the area of the quantum circuit is defined based on the depth of the quantum circuit and a number of qubits;

a hardware error rate of the quantum circuit;

a precision error of the quantum circuit;

a count of utilizations of 2-qubit gates;

a count of utilizations of gates of a predefined gate type; and

a number of qubits utilized by the quantum circuit.

11. The method of claim 1 , wherein the CSP comprises at least one of:

a variable relating to a number of auxiliary qubits available in an auxiliary pool,

a variable indicating whether an available auxiliary qubit is clean or dirty, and

a variable indicating an inter-block timing in which an auxiliary qubit is released.

12. The method of claim 1 , wherein the CSP comprises a constraint on a sub-group of functional blocks of the quantum circuit.

13. The method of claim 1 , further comprises:

compiling the gate-level representation to synthesize an executable circuit for a quantum computer; and

executing the executable circuit using the quantum computer.

14. An apparatus comprising a processor and coupled memory, said processor being adapted to:

obtain a functional-level representation of a quantum circuit, the functional-level representation comprises a first functional blocks and a second functional block, the first functional block defining a first operation of the quantum circuit over at least two cycles, the second functional block defining a second operation of the quantum circuit over at least two cycles, wherein the functional-level representation defines a relationship between the first functional block and the second functional block;

determine a Constraint Satisfaction Problem (CSP) based on the functional-level representation of the quantum circuit, wherein the CSP comprises one or more constraints based on the relationship between the first functional block and the second functional block;

automatically solve the CSP to obtain a solution to the CSP, wherein automatically solving the CSP comprises:

identifying a first implementation to the first functional block that adheres to the one or more constraints; and

identifying a second implementation to the second functional block that adheres to the one or more constraints; and

synthesize a gate-level representation of the quantum circuit using the first implementation and the second implementation.

15. The apparatus of claim 14 ,

Wherein identifying the first implementation includes selecting a first gate-level implementation of the functional block from a function library, wherein the function library comprises a pre-existing set of alternative implementations for the first functional block;

wherein the synthesizing of the gate-level representation of the quantum circuit includes inlining the first and second gate-level implementations instead of the first and second functional blocks.

16. The apparatus of claim 15 , wherein the function library defines a different valuation to a set of properties for each alternative gate-level implementation of the first functional block, wherein the first gate-level implementation is selected based on valuations of the set of properties that adhere to the one or more constraints.

17. The apparatus of claim 14 , wherein the gate-level representation comprises a set of qubits and a set of gates, wherein each gate of the set of gates defining operations on the set of qubits or portion thereof by the quantum circuit at a different cycle, wherein the gate-level representation is devoid of any block that defines a function over more than a single cycle or that is implemented using more than a single gate.

18. The apparatus of claim 14 ,

wherein the CSP defines a global constraint on a number of qubits utilized by the quantum circuit at a same cycle; and

wherein the CSP defines a global constraint on a hardware error rate of the quantum circuit.

19. The apparatus of claim 14 , wherein the CSP defines an objective function to be optimized, wherein the objective function is based on at least one of:

a depth of the quantum circuit, wherein the depth of the quantum circuit indicates a number of cycles of the quantum circuit;

an area of the quantum circuit, wherein the area of the quantum circuit is defined based on the depth of the quantum circuit and a number of qubits;

a hardware error rate of the quantum circuit;

a precision error of the quantum circuit;

a count of utilizations of 2-qubit gates;

a count of utilizations of gates of a predefined gate type; and

a number of qubits utilized by the quantum circuit.

20. A computer program product comprising a non-transitory computer readable medium retaining program instructions, which program instructions when read by a processor, cause the processor to:

obtain a directed acyclic graph representing a quantum circuit, wherein the directed acyclic graph comprises a set of blocks and connections therebetween, wherein a connection between a first block and a second block indicates passing an output value of a qubit outputted by the first block to be an input value of a qubit manipulated by the second block;

wherein the first block defining a first operation of the quantum circuit over at least two cycles, the second block defining a second operation of the quantum circuit over at least two cycles;

determine a Constraint Satisfaction Problem (CSP) based on the directed acyclic graph, wherein the CSP comprises one or more constraints based on the connections defined by the directed acyclic graph;

automatically solve the CSP to obtain a solution to the CSP, wherein said automatically solving comprises selecting an implementation to each block that adheres to the one or more constraints; and

synthesize a gate-level representation of the quantum circuit based on the solution to the CSP.