Semiconductor memory device and operation method thereof
A semiconductor memory device, includes, a cell array including a plurality of memory banks, a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory device, an address decoder receiving a read address and a write address, an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a memory bank corresponding to the write address, and an output driver configured to transmit read data output from an input/output sense amplifier of a memory bank corresponding to the read address to a read data pad, wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing. In some embodiments, the semiconductor memory device is electrically and physically coupled to a central processing unit by hybrid copper bonding.
1. A semiconductor memory device comprising:
a cell array comprising a plurality of memory banks;
a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory device;
an address decoder receiving a read address and a write address;
an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a first memory bank corresponding to the write address; and
an output driver configured to transmit read data output from an input/output sense amplifier of a second memory bank corresponding to the read address to a read data pad,
wherein the write data is input via the write data pad in a single data rate method and transmitted to the global input/output driver without deserialization processing, and the read data is transmitted from the input/output sense amplifier to the read data pad without serialization processing,
wherein the read data pad or the write data pad is electrically connected to a central processing unit by hybrid copper bonding,
wherein a first number of read data pads or a second number of write data pads corresponds to a cache line size of the central processing unit, and
wherein the read data pads comprise the read data pad and the write data pads comprise the write data pad.
2. The semiconductor memory device of claim 1 , wherein the read address and the write address are transmitted to the address decoder through different address input pads.
3. The semiconductor memory device of claim 2 , wherein the read/write command, the write address, the read address, and the write data are input during a same clock cycle.
4. The semiconductor memory device of claim 2 , wherein the write command, the write address, and the write data are input during a same clock cycle.
5. The semiconductor memory device of claim 2 , wherein the read command and the read address are simultaneously input during a same clock cycle.
6. The semiconductor memory device of claim 1 , wherein each of the input receiver and the output driver transmits the write data and the read data independently in a full duplex manner.
7. The semiconductor memory device of claim 1 , wherein the read/write command includes a read request and a write request at a same time.
8. A method of operating a semiconductor memory device connected to device central processing unit through hybrid copper bonding, the method comprising:
receiving a first command, a first write address, a first read address, and a first write data during a first clock cycle;
receiving a second command during a second clock cycle; and
outputting first read data corresponding to the first read address during the second clock cycle,
wherein a read data pad or a write data pad of the semiconductor memory device is electrically connected to the central processing unit by the hybrid copper bonding,
wherein a first number of read data pads or a second number of write data pads corresponds to a cache line size of the central processing unit, and
wherein the read data pads comprise the read data pad and the write data pads comprise the write data pad.
9. The method of claim 8 , wherein the first command comprises a read request and a write request at a same time.
10. The method of claim 8 , further comprising:
receiving a third command, a second write address, a second read address, and second write data during a third clock cycle; and
outputting second read data during the third clock cycle.
11. The method of claim 10 , wherein the semiconductor memory device comprises:
a write data path for transmitting the first write data and the second write data from a write data pad to a memory cell array; and
a read data path for transmitting the first read data and the second read data from the memory cell array to the read data pad,
wherein the write data path and the read data path are managed independently of each other.
12. The method of claim 10 , wherein the second command includes a first read request, and the third command includes a second read request and a write request at a same time.
13. A semiconductor memory device comprising:
a plurality of memory banks;
a command decoder configured to decode a read/write command, a read command, and a write command that are input from a central processing unit; and
an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a first memory bank corresponding to a write address,
wherein the write data is input during a same clock cycle as the read/write command or the write command, and
wherein the read/write command, the write address, a read address, and the write data are input during a same clock cycle.
14. The semiconductor memory device of claim 13 , further comprising:
an output driver configured to transmit read data output from an input/output sense amplifier of a second memory bank corresponding to the read address to a read data pad.
15. The semiconductor memory device of claim 14 , wherein a first number of the write data pads or a second number of the read data pads corresponds to a size of a cache line of the central processing unit, and
wherein the read data pads comprise the read data pad and the write data pads comprise the write data pad.
16. The semiconductor memory device of claim 14 , wherein the write data pad or the read data pad is connected to the central processing unit by a hybrid copper bonding.
17. The semiconductor memory device of claim 14 , wherein the write data is transferred from the write data pad to the global input/output driver without deserialization processing, and
wherein the read data is transferred from the input/output sense amplifier to the read data pad without serialization processing.
18. A semiconductor memory device comprising:
a cell array comprising a plurality of memory banks;
a command decoder configured to decode a read/write command, a read command, and a write command that are input from outside of the semiconductor memory device;
an address decoder receiving a read address and a write address;
an input receiver configured to transmit write data input through a write data pad to a global input/output driver of a first memory bank corresponding to the write address; and
an output driver configured to transmit read data output from an input/output sense amplifier of a second memory bank corresponding to the read address to a read data pad,
wherein the write data is equal in size to a single cache line once per a clock period and is input via the write data pad in a single data rate method and transmitted to the global input/output driver, and the read data is transmitted from the input/output sense amplifier to the read data pad, and
wherein a size of the single cache line is a cache line size of a central processing unit connected to the semiconductor memory device.