Non-volatile memory device
A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.
1. A non-volatile memory device comprising:
a memory cell region including first channel structures, second channel structures, first bit lines connected to the first channel structures, the first bit lines extending in a first direction, and the first bit lines being adjacent to each other in a second direction, second bit lines connected to the second channel structures, the second bit lines extending in the first direction, and the second bit lines being adjacent to each other in the second direction, a metal pattern extending in the first direction between the first bit lines and the second bit lines, and a first metal pad; and
a peripheral circuit region including a page buffer circuit and a second metal pad, and connected to the memory cell region in a vertical direction by the first metal pad and the second metal pad,
wherein the page buffer circuit includes:
first transistors arranged below the first bit lines in the vertical direction and electrically connected to the first bit lines,
second transistors arranged below the second bit lines in the vertical direction and electrically connected to the second bit lines,
a first guard ring arranged below and overlapped the metal pattern in the vertical direction, extending in the first direction, and applied with a bias voltage, and
a second guard ring extending in the second direction and applied with the bias voltage.
2. The non-volatile memory device of claim 1 , wherein the first guard ring and the second guard ring are connected to each other.
3. The non-volatile memory device of claim 1 , wherein the first guard ring and the second guard ring are spaced apart from each other.
4. The non-volatile memory device of claim 1 , wherein the first guard ring includes an active region formed in a well having a first conductivity type, and the active region having the first conductivity type, and
wherein the well is applied with the bias voltage through a contact electrically connected to the active region.
5. The non-volatile memory device of claim 1 , wherein the first guard ring includes a plurality of active regions having a first conductivity type formed in a well having the first conductivity type, and the plurality of active regions spaced apart from each other in the first direction, and
wherein the well is applied with the bias voltage through contacts electrically connected to the plurality of active regions of the first conductivity type.
6. The non-volatile memory device of claim 1 , wherein the first channel structures and second channel structures include a plurality of cell strings between the first and second bit lines and a common source line,
wherein the metal pattern corresponds to a common source line tapping wire, and
wherein the common source line tapping wire is electrically connected to the common source line.
7. The non-volatile memory device of claim 1 , wherein the memory cell region is formed in a first wafer, and
wherein the peripheral circuit region is formed in a second wafer.
8. The non-volatile memory device of claim 1 , wherein the first metal pad and the second metal pad are connected in a bonding manner.
9. The non-volatile memory device of claim 1 , wherein the page buffer circuit is arranged in a page buffer circuit region of the peripheral circuit region.
10. A non-volatile memory device comprising:
a memory cell region including a plurality of cell strings and a first metal layer, the first meal layer including a plurality of metal lines extending in a first direction, the plurality of metal lines including first bit lines adjacent to each other in a second direction, second bit lines adjacent to each other in the second direction, and a common source line tapping wire between the first bit lines and the second bit lines; and
a page buffer circuit arranged below the memory cell region in a vertical direction,
wherein the page buffer circuit includes a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction,
wherein each of the plurality of cell strings has a plurality of memory cells, wherein the plurality of cell strings are disposed between the first and second bit lines and a common source line, and
wherein the common source line tapping wire is electrically connected to the common source line.
11. The non-volatile memory device of claim 10 , wherein the memory cell region further includes:
a first cell region in which a plurality of first channel structures are arranged;
a second cell region in which a plurality of second channel structures are arranged; and
a cut-off region between the first cell region and the second cell region, and
wherein the first bit lines and the second bit lines are electrically connected to the page buffer circuit through a plurality of through electrodes arranged in the cut-off region.
12. The non-volatile memory device of claim 11 , wherein the common source line tapping wire is connected to the common source line through a plurality of through electrodes arranged in the first cell region and the second cell region.
13. The non-volatile memory device of claim 10 , wherein the first guard ring is applied with a bias voltage.
14. A non-volatile memory device comprising:
a memory cell region including first channel structures, second channel structures, first bit lines connected to the first channel structures, the first bit lines extending in a first direction, and the first bit lines being adjacent to each other in a second direction, second bit lines connected to the second channel structures, the second bit lines extending in the first direction, and the second bit lines being adjacent to each other in the second direction, a metal pattern extending in the first direction between the first bit lines and the second bit lines, and a first metal pad; and
a peripheral circuit region including a page buffer circuit and a second metal pad, and connected to the memory cell region in a vertical direction by the first metal pad and the second metal pad,
wherein the page buffer circuit includes:
first transistors arranged below the first bit lines in the vertical direction and electrically connected to the first bit lines,
second transistors arranged below the second bit lines in the vertical direction and electrically connected to the second bit lines, and
a first guard ring arranged below and overlapped the metal pattern in the vertical direction and arranged in a diagonal direction.
15. The non-volatile memory device of claim 14 , wherein first guard ring is arranged in an inclined manner according to an arrangement of an adjacent active region and a gate electrode of at least one of the first transistors and the second transistors.
16. The non-volatile memory device of claim 14 , wherein the first guard ring is arranged to have an angle with respect to the second direction.
17. The non-volatile memory device of claim 16 , wherein the angle is between 45 and 90 degrees.
18. The non-volatile memory device of claim 14 , wherein the page buffer circuit further includes a second guard ring arranged below the metal pattern in the vertical direction and extending in the first direction, and
wherein the first and second guard rings are apart from each other in the first direction.
19. The non-volatile memory device of claim 18 , wherein the page buffer circuit further includes a third guard ring arranged below the metal pattern in the vertical direction and extending in the first direction, and
wherein the second and third guard rings are partially in contact with each other in the second direction.
20. The non-volatile memory device of claim 14 , wherein the first guard ring is applied with a bias voltage.