IP Library › Granted Patent US 12,381,298
Granted Patent B2
US 12,381,298 · App. 18/770,206 · Granted Aug 5, 2025

Superconducting qubit memory of quantum computer

Inventors: Jaehyeong Lee (Gwacheon-si, KR); Hyeokshin Kwon (Seoul, KR); Jaeho Shin (Cheonan-si, KR); Taehwan Jang (Suwon-si, KR); Insu Jeon (Seoul, KR)
Assignee: SAMSUNG ELECTRONICS CO., LTD.
H01P3/003G06N10/00H01P7/086
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Quick Facts
Patent No.
US 12,381,298
App. No.
18/770,206
Granted
Aug 5, 2025
Kind
B2
Abstract

A qubit memory of a quantum computer is provided. The qubit memory according to an embodiment includes a first readout unit, a first transmon, and a first data storage unit storing quantum information, and the first data storage unit includes a first superconducting waveguide layer, an insulating layer, and a superconductor layer sequentially stacked on a substrate. In one example, the first superconducting waveguide layer may include a superconducting resonator.

Claims (28)

1. A qubit memory of a quantum computer, the qubit memory comprising:

a first qubit memory,

wherein the first qubit memory comprises a first data storage unit configured to store quantum information,

wherein the first data storage unit comprises:

a substrate; and

a plurality of superconducting waveguide layers which are separated from each other and vertically stacked on the substrate, and

wherein the first data storage unit further comprises an insulating layer and a superconductor layer that are between the plurality of superconducting waveguide layers.

2. The qubit memory of claim 1 , wherein each of the plurality of superconducting waveguide layers comprises a superconducting resonator.

3. The qubit memory of claim 1 , wherein a first superconducting waveguide layer of the plurality of superconducting waveguide layers has a thickness in a range from about 50 nm to about 100 nm.

4. The qubit memory of claim 1 , wherein the superconductor layer has a thickness in a range from about 50 nm to about 100 nm.

5. The qubit memory of claim 1 , wherein the insulating layer continuously extends onto the superconductor layer and covers an entire upper surface of the superconductor layer.

6. The qubit memory of claim 1 , wherein the first data storage unit comprises a plurality of stack structures, and

wherein each of the plurality of stack structures comprises the insulating layer, the superconductor layer and one of the superconducting waveguide layers.

7. The qubit memory of claim 6 , wherein some stack structures from among the plurality of stack structures have a first buried shape of the superconductor layer in the insulating layer,

wherein the remaining stack structures from among the plurality of stack structures have a second buried shape of the superconductor layer in the insulating layer, and

wherein the second buried shape is different from the first buried shape.

8. The qubit memory of claim 1 , wherein the first qubit memory further comprises:

a readout unit; and

a transmon.

9. The qubit memory of claim 1 , further comprising a second qubit memory comprising a second data storage unit.

10. A quantum computer comprising:

a qubit memory comprising:

a first qubit memory,

wherein the first qubit memory comprises a first data storage unit configured to store quantum information,

wherein the first data storage unit comprises:

a substrate; and

a plurality of superconducting waveguide layers which are separated from each other and vertically stacked on the substrate, and

wherein the first data storage unit further comprises an insulating layer and a superconductor layer that are between the plurality of superconducting waveguide layers.

Priority Claims (1)
KR 10-2020-0150514 · Nov 11, 2020 · national
Continuity (2)
Continuation 17515055 · Oct 29, 2021
Related Publication 20240363989A1 · Oct 31, 2024
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