Semiconductor integrated circuit
Provided are a semiconductor integrated circuit and an imaging device capable of reducing power consumption without complicating a configuration of oscillation control. A semiconductor integrated circuit includes an oscillator that generates an oscillation signal whose oscillation frequency is discretely adjustable on the basis of a digital control input signal, an oscillation controller that generates the digital control input signal, and an intermittent controller that generates an intermittent control signal and supplies the intermittent control signal to the oscillation controller so that the oscillation controller intermittently updates the digital control input signal.
1. A semiconductor integrated circuit, comprising:
an oscillation controller configured to generate a digital control input signal,
an oscillator configured to generate a first oscillation signal, wherein
a first oscillation frequency of the first oscillation signal is adjustable, and
the oscillation controller is further configured to adjust the first oscillation frequency based on the generated digital control input signal;
a sensor configured to generate a first signal, wherein the sensor includes:
a pixel array unit that includes a plurality of pixels, wherein
each pixel of the plurality of pixels is configured to perform photoelectric conversion,
each pixel of the plurality of pixels includes a read circuit, and
the read circuit is configured to read a photoelectric converted signal; and
a timing controller configured to:
control a first timing associated with the photoelectric conversion; and
control a second timing associated with the read photoelectric converted signal; and
an intermittent controller configured to:
generate an intermittent control signal; and
transmit the intermittent control signal to the oscillation controller, wherein
the oscillation controller is further configured to intermittently update the digital control input signal based on the intermittent control signal.
2. The semiconductor integrated circuit according to claim 1 , wherein
the oscillation controller is further configured to hold the updated digital control input signal in a specific period, and
the specific period corresponds to a time in which the digital control input signal is not updated.
3. The semiconductor integrated circuit according to claim 1 , wherein
the intermittent controller is further configured to generate the intermittent control signal based on the generated first signal.
4. The semiconductor integrated circuit according to claim 1 , wherein
the sensor is further configured to perform a sensing operation based on the first oscillation signal, and
the intermittent controller is further configured to generate the intermittent control signal based on the generated first signal.
5. The semiconductor integrated circuit according to claim 4 , wherein
the timing controller is further configured to generate a second signal, and
the intermittent controller is further configured to generate the intermittent control signal based on the generated second signal.
6. The semiconductor integrated circuit according to claim 5 , wherein
the plurality of pixels is in a horizontal direction and a vertical direction in the pixel array unit,
the timing controller is further configured to generate a horizontal synchronization signal and a vertical synchronization signal,
the read circuit is further configured to read the photoelectric converted signal based on the horizontal synchronization signal and the vertical synchronization signal, and
the intermittent controller is further configured to generate the intermittent control signal based on at least one of the horizontal synchronization signal or the vertical synchronization signal.
7. The semiconductor integrated circuit according to claim 6 , wherein
the plurality of pixels includes a valid pixel and an invalid pixel,
the oscillation controller is further configured to update the digital control input signal in a specific period,
the specific period includes a first signal output period,
the first signal output period is associated with the invalid pixel, and
after a lapse of the specific period, the oscillation controller is further configured to stop the update of the digital control input signal until a second signal output period of the invalid pixel, wherein the second signal output period is after the first signal output period.
8. The semiconductor integrated circuit according to claim 7 , wherein the specific period is longer than the first signal output period of the invalid pixel.
9. The semiconductor integrated circuit according to claim 6 , wherein
the plurality of pixels includes a valid pixel and an invalid pixel,
the oscillation controller is further configured to update the digital control input signal in a first period and in a second period,
the first period includes a first signal output period of the invalid pixel, and
the second period includes a second signal output period of the valid pixel.
10. The semiconductor integrated circuit according to claim 9 , wherein
the second signal output period includes a plurality of second periods, and
the plurality of second periods includes the second period.
11. The semiconductor integrated circuit according to claim 4 , further comprising:
a frequency divider configured to:
divide the first oscillation frequency of the first oscillation signal; and
generate a second oscillation frequency based on the division of the first oscillation frequency, wherein
the sensor is further configured to perform the sensing operation based on the second oscillation frequency.
12. The semiconductor integrated circuit according to claim 4 , further comprising:
a performance evaluator configured to:
generate an evaluation signal;
evaluate a performance of the sensor based on the generated evaluation signal; and
an update controller configured to control a specific period and a specific frequency, wherein
the oscillation controller is further configured to update the digital control input signal based on the evaluation signal,
each of the specific period and the specific frequency is associated with the updated digital control input signal, and
the intermittent controller is further configured to generate the intermittent control signal based on the specific period and the specific frequency.
13. The semiconductor integrated circuit according to claim 3 , wherein the first signal includes a spread spectrum clock control signal.
14. The semiconductor integrated circuit according to claim 1 , further comprising
a spread spectrum clocking (SSC) controller configured to generate a spread spectrum clock control signal, wherein
the oscillator is further configured to adjust the first oscillation frequency based on the digital control input signal and the spread spectrum clock control signal, and
the intermittent controller is further configured to generate the intermittent control signal based on the spread spectrum clock control signal.
15. The semiconductor integrated circuit according to claim 14 , wherein
the spread spectrum clock control signal includes a periodic signal,
the oscillation controller is further configured to update the digital control input signal in a specific period, and
a cycle of the spread spectrum clock control signal includes the specific period.
16. The semiconductor integrated circuit according to claim 15 , wherein
the specific period includes at least one of a peak of a signal level or a bottom of the signal level, and
the signal level is associated with the spread spectrum clock control signal.
17. A semiconductor integrated circuit, comprising:
a first oscillation controller configured to generate a first digital control input signal;
a first oscillator configured to generate a first oscillation signal, wherein
a first oscillation frequency associated with the first oscillation signal is adjustable, and
the first oscillation controller is further configured to adjust the first oscillation frequency based on the generated first digital control input signal;
a first intermittent controller configured to:
generate a first intermittent control signal; and
transmit the first intermittent control signal to the first oscillation controller, wherein
the first oscillation controller is further configured to intermittently update the first digital control input signal based on the first intermittent control signal;
a second oscillation controller configured to generate a second digital control input signal;
a second oscillator configured to generate a second oscillation signal, wherein
a second oscillation frequency of the second oscillation signal is adjustable,
the second oscillation controller is further configured to adjust the second oscillation frequency based on the generated second digital control input signal;
a spread spectrum clocking (SSC) controller configured to generate a spread spectrum clock control signal; and
a second intermittent controller configured to:
generate a second intermittent control signal; and
transmit the second intermittent control signal to the second oscillation controller, wherein
the second oscillation controller is further configured to intermittently update the second digital control input signal,
the second oscillator is further configured to adjust the second oscillation frequency based on the second digital control input signal and the spread spectrum clock control signal, and
the second intermittent controller is further configured to generate the second intermittent control signal based on the spread spectrum clock control signal.
18. A semiconductor integrated circuit, comprising:
a first oscillation controller configured to generate a first digital control input signal;
a first oscillator configured to generate a first oscillation signal, wherein
a first oscillation frequency of the first oscillation signal is adjustable, and
the first oscillation controller is further configured to adjust the first oscillation frequency based on the generated first digital control input signal;
a sensor configured to generate a first signal, wherein the sensor includes:
a pixel array unit that includes a plurality of pixels, wherein each pixel of the plurality of pixels is configured to perform photoelectric conversion; and
a timing controller configured to control a first timing associated with the photoelectric conversion;
a first intermittent controller configured to:
generate a first intermittent control signal; and
transmit the first intermittent control signal to the first oscillation controller, wherein
the first oscillation controller is further configured to intermittently update the first digital control input signal;
a signal transmitter configured to perform a signal transmission based on the first oscillation signal; and
a first controller configured to control a second timing, wherein
the first intermittent controller is further configured to generate, in the second timing, the first intermittent control signal based on an operation mode of the signal transmitter.
19. The semiconductor integrated circuit according to claim 18 , comprising:
a second oscillation controller configured to generate a second digital control input signal;
a second oscillator configured to generate a second oscillation signal, wherein
a second oscillation frequency of the second oscillation signal is adjustable, and
the second oscillation controller is further configured to adjust the second oscillation frequency based on the generated second digital control input signal;
a second intermittent controller configured to:
generate a second intermittent control signal; and
transmit the second intermittent control signal to the second oscillation controller, wherein
the second oscillation controller is further configured to intermittently update the second digital control input signal;
a signal processor configured to perform a signal processing based on the second oscillation signal; and
a second controller configured to control a third timing, wherein
the second intermittent controller is further configured to generate, in the third timing, the second intermittent control signal based on an operation mode of the signal processor.
20. The semiconductor integrated circuit according to claim 18 , comprising:
a frequency divider configured to:
divide the first oscillation frequency of the first oscillation signal; and
generate a second oscillation signal based on the division of the first oscillation frequency;
a signal processor configured to perform a signal processing based on the generated second oscillation signal; and
a second controller configured to intermittently control the frequency divider based on an operation mode of the signal processor.