Efficient TLV style header parsing and editing
In some aspects, the disclosure is directed to methods and systems for a flexible type-length-value (TLV) parser and identification map that may be used to quickly identify TLV sequences of packet headers for subsequent processing in a pipeline. A flexible TLV bus may provide a secondary path for the TLV header and identification map, allowing for subsequent processing stages to read, process, modify, delete, or otherwise utilize individual TLV sequences within the header.
1. A method comprising:
identifying, by a type-length-value (TLV) processor of a device, a type of a TLV sequence of one or more TLV sequences present in a header of a packet and a starting location of the header, the packet received via communications over one or more networks;
determining, by the TLV processor, an offset of a location of the TLV sequence in the header based at least on the starting location;
encoding, by the TLV processor, the TLV sequence in a bitmap using the type and offset; and
providing, by the TLV processor, the bitmap for use by another TLV processor to identify the TLV sequence in the header.
2. The method of claim 1 , further comprising receiving, by the TLV processor, the packet from a packet data bus.
3. The method of claim 1 , further comprising determining, by the TLV processor, that the TLV sequence is present in the TLV header of the packet, wherein the TLV header is configured at a layer in a network stack of the device having a network interface to receive the packet via the one or more networks.
4. The method of claim 1 , further comprising generating, by the TLV processor, the bitmap to identify the one or more TLV sequences within the header.
5. The method of claim 1 , further comprising encoding, by the TLV processor, the TLV sequence in the bitmap using a tuple comprising at least the type and the offset.
6. The method of claim 1 , wherein the TLV processor comprises a packet processing engine configured on one or more processors.
7. The method of claim 1 , wherein the TLV processor comprises circuitry.
8. The method of claim 1 , further comprising placing, by the TLV processor, the bitmap on a flex bus for another TLV processor to use.
9. A system comprising:
a device configured with a type-length-value (TLV) processor, the device having a network interface configured to receive one or more packets via communications over one or more networks;
the TLV processor configured to:
identify a type of a TLV sequence of one or more TLV sequences present in a header of a packet and a starting location of the header;
determine an offset of a location of the TLV sequence in the header based at least on the starting location;
encode the TLV sequence in a bitmap using the type and offset; and
communicate the bitmap on a bus for use by another TLV processor to identify the TLV sequence in the header.
10. The system of claim 9 , wherein the TLV processor is further configured to receive the packet from a packet data bus.
11. The system of claim 9 , wherein the TLV processor is further configured to determine that the TLV sequence is present in the TLV header of the packet, wherein the TLV header is configured at a layer in a network stack of the device having a network interface to receive the packet via the one or more networks.
12. The system of claim 9 , wherein the TLV processor is further configured to generate the bitmap to encode the one or more TLV sequences within the header.
13. The system of claim 9 , wherein the TLV processor is further configured to encode the TLV sequence in the bitmap using a tuple comprising at least the type and the offset.
14. The system of claim 9 , wherein the TLV processor comprises a packet processing engine configured on one or more processors.
15. The system of claim 9 , wherein the TLV processor comprises circuitry.
16. A device comprising:
circuitry providing a type-length-value (TLV) circuit;
the TLV circuit configured to:
identify a type of a TLV sequence of one or more TLV sequences present in a header of a packet and a starting location of the header;
determine an offset of a location of the TLV sequence in the header based at least on the starting location;
encode the TLV sequence in a bitmap using the type and offset; and
place the bitmap on a bus for use by another TLV circuit to identify the TLV sequence in the header.
17. The device of claim 16 , wherein the TLV circuit is further configured to receive the packet from a packet data bus.
18. The device of claim 16 , wherein the TLV circuit is further configured to determine that the TLV sequence is present in the TLV header of the packet.
19. The device of claim 16 , wherein the TLV circuit is further configured to generate the bitmap and encode the TLV sequence in the bitmap using a tuple comprising at least the type and the offset.
20. The device of claim 16 , wherein the TLV circuit and the another TLV circuit is electrically coupled to the bus.