Video frame codec architectures
Techniques and apparatuses are described for video frame codec architectures. A frame decompressor decompresses compressed frames to produce decompressed frames. A frame decompressor controller arbitrates shared access to the frame decompressor. Multiple cores of an SoC request to receive a decompressed frame from the frame decompressor via the frame decompressor controller. The frame decompressor controller can implement a request queue and can order the servicing of requests based on priority of the requests or requesting cores. The frame decompressor controller can also establish a time-sharing protocol for access by the multiple cores. In some implementations, a video decoder is logically integrated with the frame decompressor and stores portions of a decompressed frame in a video buffer, and a display controller retrieves the portions for display using a synchronization mechanism. In analogous manners, a frame compressor controller can arbitrate shared access to a frame compressor for the multiple cores.
1. An electronic device comprising:
a frame compressor configured to individually compress at a frame-level multiple uncompressed frames to produce multiple compressed frames, the multiple uncompressed frames respectively corresponding to multiple decoded frames;
a frame compressor controller coupled to the frame compressor and configured to arbitrate access to the frame compressor for multiple cores;
a first core of the multiple cores coupled to the frame compressor controller, the first core configured to obtain via the frame compressor controller a compressed frame of the multiple compressed frames produced at the frame-level by the frame compressor; and
a second core of the multiple cores coupled to the frame compressor controller, the second core configured to obtain via the frame compressor controller another compressed frame of the multiple compressed frames produced at the frame-level by the frame compressor.
2. The electronic device of claim 1 , wherein:
the first core is configured to use the compressed frame for a first video-related purpose;
the second core is configured to use the other compressed frame for a second video-related purpose; and
the first video-related purpose and the second video-related purpose comprise different video-related purposes selected from a group of video-related purposes including: video decoding, video encoding, video displaying, video transcoding, or video compensating.
3. The electronic device of claim 1 , wherein:
the first core comprises a video decoder configured to decode a video stream to produce the multiple decoded frames;
the frame compressor is logically integrated with the video decoder; and
the second core comprises a display controller.
4. The electronic device of claim 1 , wherein:
the first core comprises a video decoder configured to decode a video stream to produce the multiple decoded frames; and
the second core comprises a video encoder configured to encode the multiple uncompressed frames into another video stream.
5. The electronic device of claim 1 , wherein the frame compressor controller comprises:
a request queue configured to store multiple requests, each request corresponding to at least one compressed frame; and
a request manager configured to receive the multiple requests from the multiple cores and to insert the multiple requests into the request queue.
6. The electronic device of claim 1 , wherein the frame compressor controller comprises a time-sharing protocol handler configured to establish a time-sharing protocol to share the frame compressor between the multiple cores.
7. The electronic device of claim 6 , wherein the time-sharing protocol handler is configured to at least one of:
establish the time-sharing protocol to include multiple timeslots that are assigned to at least one core of the multiple cores; or
establish the time-sharing protocol to permit reception of an interrupt signal from a core of the multiple cores, the interrupt signal indicative of a request for at least one compressed frame.
8. The electronic device of claim 1 , further comprising:
a frame decompressor configured to individually decompress at the frame-level one or more compressed frames to produce one or more decompressed frames; and
a frame decompressor controller coupled to the frame decompressor and configured to arbitrate access to the frame decompressor for the multiple cores.
9. The electronic device of claim 8 , further comprising:
a video buffer associated with the frame decompressor; and
a synchronization register corresponding to the video buffer, the synchronization register configured to store one or more values indicative of a status of contents of the video buffer, wherein:
the frame decompressor is configured to store in the video buffer at least a portion of at least one decompressed frame of the one or more decompressed frames; and
the frame decompressor controller is configured to write into the synchronization register at least one value indicative of the status of the stored portion.
10. The electronic device of claim 1 , wherein the frame compressor is configured to individually compress at the frame-level the multiple decoded frames to produce at least a portion of the multiple compressed frames.
11. The electronic device of claim 1 , wherein the frame compressor is configured to implement a lossless frame-level compression algorithm to produce the multiple compressed frames respectively from the multiple uncompressed frames.
12. An electronic device comprising:
a frame compressor configured to compress multiple uncompressed frames to produce multiple compressed frames;
a frame compressor controller coupled to the frame compressor and configured to arbitrate access to the frame compressor for multiple cores, the frame compressor controller comprising a time-sharing protocol handler configured to establish a time-sharing protocol to share the frame compressor between the multiple cores, the time-sharing protocol handler configured to at least one of:
establish the time-sharing protocol to include multiple timeslots that are assigned to at least one core of the multiple cores; or
establish the time-sharing protocol to permit reception of an interrupt signal from a core of the multiple cores, the interrupt signal indicative of a request for at least one compressed frame;
a first core of the multiple cores coupled to the frame compressor controller, the first core configured to obtain via the frame compressor controller a compressed frame of the multiple compressed frames produced by the frame compressor; and
a second core of the multiple cores coupled to the frame compressor controller, the second core configured to obtain via the frame compressor controller another compressed frame of the multiple compressed frames produced by the frame compressor.
13. A method for sharing frame compression circuitry between multiple cores, the method comprising:
decoding at least one video stream to produce multiple decoded frames, the multiple decoded frames corresponding to a first uncompressed frame and a second uncompressed frame;
accepting, from a first core, a first request for a first compressed frame;
individually compressing at a frame-level the first uncompressed frame to produce the first compressed frame;
providing, to the first core, the first compressed frame responsive to the first request;
accepting, from a second core, a second request for a second compressed frame;
individually compressing at the frame-level the second uncompressed frame to produce the second compressed frame; and
providing, to the second core, the second compressed frame responsive to the second request.
14. The method of claim 13 , further comprising:
accepting, from a third core, a third request for a third compressed frame;
individually compressing at the frame-level a third uncompressed frame to produce the third compressed frame; and
providing, to the third core, the third compressed frame responsive to the third request, wherein:
the first request is indicative of the first core;
the second request is indicative of the second core; and
the third request is indicative of the third core.
15. The method of claim 13 , further comprising:
establishing a time-sharing protocol for access to the frame compression circuitry by at least the first core and the second core.
16. The method of claim 15 , wherein the establishing comprises:
receiving, during a timeslot that corresponds to the first core, an interrupt from the second core; and
responsive to receipt of the interrupt, switching from performing compression for the first core to performing compression for the second core.
17. The method of claim 13 , further comprising:
performing the providing of the first compressed frame and the providing of the second compressed frame in an order that is at least partially dependent on a relative priority between the first request and the second request.
18. The method of claim 13 , further comprising:
accepting, from at least a portion of the multiple cores, multiple requests for respective ones of multiple decompressed frames;
decompressing multiple compressed frames to respectively produce the multiple decompressed frames; and
providing, to at least the portion of the multiple cores, the multiple decompressed frames responsive to the multiple requests.
19. The method of claim 18 , wherein:
a decompressed frame of the multiple decompressed frames comprises a line and an additional line; and
the method further comprises providing the decompressed frame to a core of the multiple cores by:
polling a synchronization register to obtain at least one value indicative of a read status of the line with respect to a video buffer; and
responsive to the at least one value, storing the additional line into the video buffer.
20. The method of claim 13 , wherein:
the first uncompressed frame comprises or is derived from a first decoded frame of the multiple decoded frames; and
the second uncompressed frame comprises or is derived from a second decoded frame of the multiple decoded frames.