Semiconductor structure and manufacturing method thereof
View Patent ↗The present disclosure relates to the technical field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes: a base, and bit lines, word lines, active pillars, and a memory structure that are located on the base. The bit line extends along a first direction, the word line extends along a second direction, the first direction is one of a direction perpendicular to a surface of the base or a direction parallel to the surface of the base, and the second direction is the other of the direction perpendicular to the surface of the base or the direction parallel to the surface of the base. The active pillars are parallel to the base and arranged at intervals, the word line surrounds a channel region of the active pillar, the memory structure surrounds a support region of the active pillar.
1. A semiconductor structure, comprising:
a base, and a plurality of bit lines, a plurality of word lines, a plurality of active pillars, and a plurality of capacitor structures that are located on the base;
wherein the plurality of bit lines extends along a first direction, the plurality of word lines extends along a second direction, the first direction is perpendicular to a surface of the base, and the second direction is parallel to the surface of the base; and
the plurality of active pillars are parallel to the base and arranged at intervals, each of the plurality of word lines surrounds a channel region of one of the plurality of active pillars, one of a source region or a drain region of each of the plurality of active pillars is electrically connected to one of the plurality of bit lines, the other of the source region or the drain region of each of the plurality of active pillars is electrically connected to one of the plurality of capacitor structures, each of the plurality of capacitor structures surrounds a support region of one of the plurality of active pillars, and the support region is located at one end of the source region or the drain region, that is connected to one of the plurality of capacitor structures, of each of the plurality of active pillars.
2. The semiconductor structure according to claim 1 , wherein one of the plurality of word lines, the channel region, and the source region and the drain region that are located at two ends of the channel region constitute a transistor structure; and along a direction pointing from the source region to the drain region, at least two transistor structures are provided, and the at least two transistor structures are electrically connected to one of the plurality of bit lines.
3. The semiconductor structure according to claim 1 , further comprising:
an insulating layer, wherein the insulating layer is located between the plurality of word lines and the plurality of bit lines; and
a medium layer, wherein the medium layer is located between the plurality of word lines and the insulating layer and between the plurality of word lines and the channel region.
4. The semiconductor structure according to claim 1 , further comprising: an isolation layer, wherein the isolation layer is located between adjacent ones of the plurality of active pillars.
5. The semiconductor structure according to claim 1 , wherein a material of the plurality of active pillars comprises an amorphous material.
6. The semiconductor structure according to claim 5 , wherein the amorphous material comprises at least one of indium gallium zinc oxide, indium tin oxide, indium gallium zinc tin oxide, or indium tungsten oxide.