Granted Patent B2

US 12,386,669 · App. 17/541,016 · Granted Aug 12, 2025

Inventors: Niranjan Hasabnis (Fremont, CA); Justin Gottschlich (Santa Clara, CA); Jesmin Jahan Tithi (San Jose, CA); Anand Venkat (San Jose, CA)

Assignee: Intel Corporation

G06F9/5044G06F9/30101G06F9/3836G06F9/4552G06F9/5016G06F9/5038

Abstract

Claims (80)

1. An apparatus to generate a mapping table based on execution cost, the apparatus comprising:

memory;

instructions included in the apparatus; and

processor circuitry to execute the instructions to:

convert a plurality of instructions into mnemonics and operands;

generate converted instructions by replacing the operands with corresponding tokens;

generate unique pairs by combining respective ones of the plurality of instructions with the corresponding converted instructions;

execute a portion of the plurality of instructions corresponding to a mnemonic, the portion of the plurality of instructions selected from the generated pairs;

determine an average execution cost of the portion of the plurality of instructions;

determine a standard deviation of execution costs of the portion of the plurality of instructions; and

generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

2. The apparatus of claim 1 , wherein the processor circuitry is to execute the portion of the plurality of instructions on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

3. The apparatus of claim 1 , wherein the processor circuitry is to:

store the unique pairs in the memory; and

access the portion of the plurality of instructions corresponding to the mnemonic from the memory.

4. The apparatus of claim 1 , wherein the processor circuitry is to:

determine whether a pair including at least one of a same mnemonic or a same operand is included in storage; and

when the pair is already included in the storage, discard the pair.

5. The apparatus of claim 1 , wherein the token corresponds to at least one of a constant type when the operand corresponds to a numeric constant or a register when the operand corresponds to a register operation.

6. The apparatus of claim 1 , wherein the processor circuitry is to:

obtain the instructions from a repository; and

convert the instructions into assembly language.

7. A non-transitory computer readable medium comprising instructions which, when executed, cause one or more processors to at least:

convert a plurality of instructions into mnemonics and operands;

generate converted instructions by replacing the operands with corresponding tokens;

generate unique pairs by combining respective ones of the plurality of instructions with the corresponding converted instructions;

execute a portion of the plurality of instructions corresponding to a mnemonic, the portion of the plurality of instructions selected from the generated pairs;

determine an average execution cost of the portion of the plurality of instructions;

determine a standard deviation of execution costs of the portion of the plurality of instructions; and

generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

8. The computer readable medium of claim 7 , wherein the instructions cause the one or more processors to execute the portion of the plurality of instructions on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

9. The computer readable medium of claim 8 , wherein the instructions cause the one or more processors to:

store the unique pairs in storage; and

access the portion of the plurality of instructions corresponding to the mnemonic from the storage.

10. The computer readable storage medium of claim 8 , wherein the instructions cause the one or more processors to:

determine whether a pair including at least one of a same mnemonic or a same operand is included in storage; and

when the pair is already included in the storage, discard the pair.

11. The computer readable medium of claim 8 , wherein the token corresponds to at least one of a constant type when the operand corresponds to a numeric constant or a register when the operand corresponds to a register operation.

12. The computer readable medium of claim 7 , wherein the instructions cause the one or more processors to:

obtain the instructions from a repository; and

convert the instructions into assembly language.

13. An apparatus to generate a mapping table based on execution cost, the apparatus comprising:

interface circuitry; and

processor circuitry including one or more of:

at least one of a central processing unit, a graphic processing unit or a digital signal processor, the at least one of the central processing unit, the graphic processing unit or the digital signal processor having control circuitry, one or more registers, and arithmetic and logic circuitry to perform one or more first operations corresponding to instructions in the apparatus, and;

a Field Programmable Gate Array (FPGA), the FPGA including logic gate circuitry, a plurality of configurable interconnections, and storage circuitry, the logic gate circuitry and interconnections to perform one or more second operations; or

Application Specific Integrate Circuitry (ASIC) including logic gate circuitry to perform one or more third operations;

the processor circuitry to perform at least one of the first operations, the second operations or the third operations to instantiate:

instruction converter circuitry to:

convert a plurality of instructions into mnemonics and operands;

generate converted instructions by replacing the operands with corresponding tokens;

generate unique pairs by combining respective ones of the plurality of instructions with the corresponding converted instructions;

cost mapping circuitry to:

execute a portion of the plurality of instructions corresponding to a mnemonic, the portion of the plurality of instructions selected from the generated pairs;

determine an average execution cost of the portion of the plurality of instructions;

determine a standard deviation of execution costs of the portion of the plurality of instructions; and

generate a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

14. The apparatus of claim 13 , wherein the cost mapping circuitry is to execute the portion of the plurality of instructions on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

15. The apparatus of claim 13 , wherein:

the instruction converter circuitry is to store the unique pairs in storage; and

the cost mapping circuitry is to access the portion of the plurality of instructions corresponding to the mnemonic from the storage.

16. The apparatus of claim 13 , wherein the cost mapping circuitry is to:

determine whether a pair including at least one of a same mnemonic or a same operand is included in storage; and

when the pair is already included in the storage, discard the pair.

17. The apparatus of claim 13 , wherein the token corresponds to at least one of a constant type when the operand corresponds to a numeric constant or a register when the operand corresponds to a register operation.

18. The apparatus of claim 13 , further including an architecture-specific compiler to:

obtain the instructions from a repository; and

convert the instructions into assembly language.

19. A method to generate a mapping table based on execution cost, the method comprising:

converting, by executing an instruction with one or more processors, a plurality of instructions into mnemonics and operands;

generating, by executing an instruction with the one or more processors, converted instructions by replacing the operands with corresponding tokens;

generating, by executing an instruction with the one or more processors, unique pairs by combining respective ones of the plurality of instructions with the corresponding converted instructions;

executing a portion of the plurality of instructions corresponding to a mnemonic, the portion of the plurality of instructions selected from the generated pairs;

determining, by executing an instruction with the one or more processors, an average execution cost of the portion of the plurality of instructions;

determining, by executing an instruction with the one or more processors, a standard deviation of execution costs of the portion of the plurality of instructions; and

generating, by executing an instruction with the one or more processors, a mapping table including an entry, the entry including the mnemonic in association with the average and the standard deviation.

20. The method of claim 19 , further including executing the portion of the plurality of instructions on a processor unit specific to an architecture, the architecture corresponding to a computing device that obtains the mapping table to estimate execution cost.

21. The method of claim 19 , further including:

storing the unique pairs in storage; and

accessing the portion of the plurality of instructions corresponding to the mnemonic from the storage.

Assignments (1)

Continuity (1)

References Cited (20)