Controller and method of operating the same
A controller controls a semiconductor memory device including a plurality of pages. The controller includes a command generator configured to generate a command for controlling a program operation or a read operation of a semiconductor memory device, and a data recovery manager configured to generate parity data corresponding to a weak page among a plurality of pages included in the semiconductor memory device and recover data programmed to the weak page.
1. A controller comprising:
a processing unit configured to:
generate a command for controlling a program operation or a read operation of a semiconductor memory device;
generate parity data corresponding to a weak page among a plurality of pages included in the semiconductor memory device, the weak page is an i-th page; and
recover data programmed in the weak page based on the parity data, and
a data storage configured to store the parity data,
wherein the processing unit generates the parity data by performing an exclusive-OR (XOR) operation on data programmed in the weak page and data programmed in an (i−1)-th page.
2. The controller of claim 1 , wherein the processing unit
generates the parity data by performing an exclusive-OR (XOR) operation on the data programmed in the weak page, the data programmed in the (i−1)-th page and data programmed in an (i+1)-th page.
3. The controller of claim 1 , wherein the processing unit generates the command for controlling the semiconductor memory device to program the parity data to a memory block different from a memory block including the weak page.
4. The controller of claim 1 , wherein the processing unit stores
a weak page information for identifying weak pages among the plurality of pages
and the parity data in the data storage.
5. The controller of claim 1 , wherein the processing unit
generates the command for controlling the semiconductor memory device to read data stored in the weak page, and
recovers the data programmed in the weak page based on the parity data and the data programmed in pages adjacent to the weak page when an uncorrectable error is included in the data programmed in the weak page.
6. The controller of claim 5 , wherein the processing unit
recovers the data programmed in the weak page by performing an exclusive-OR (XOR) operation on the parity data and the data programmed in the pages adjacent to the weak page.
7. A method of operating a controller, the method comprising:
determining whether to program data to a selected page among a plurality of pages included in a semiconductor memory device;
determining whether the selected page is a weak page; and
generating parity data based on data programmed in the selected page and data programmed in one or more pages adjacent to the selected page when the selected page is determined as the weak page,
wherein the generating the parity data comprises:
determining a page adjacent to the weak page is an (i−1)-th page when the weak page is an i-th page; and
generating the parity data by performing an exclusive-OR (XOR) operation on data programmed in the page adjacent to the weak page and data programmed in the weak page.
8. The method of claim 7 , wherein the generating the parity data comprises:
determining pages adjacent to the weak page are (i−1)-th and (i+1)-th pages when the weak page is an i-th page; and
generating the parity data by performing an exclusive-OR (XOR) operation on data programmed in the pages adjacent to the weak page and the data programmed in the weak page.
9. The method of claim 7 , further comprising storing the parity data in the controller.
10. The method of claim 7 , further comprising controlling the semiconductor memory device to program the parity data to a memory block different from a memory block including the weak page.
11. The method of claim 10 , wherein the memory block different from the memory block including the weak page includes single-level cells (SLCs).
12. A method of operating a controller, the method comprising:
controlling a semiconductor memory device to read data programmed in a weak page among a plurality of pages included in the semiconductor memory device, the weak page is an i-th page;
receiving the read data from the semiconductor memory device and performing an error correction operation on the received data;
obtaining parity data associated with the weak page and data programmed in one or more pages adjacent to the weak page when error correction of the received data is determined as failed; and
recovering the data programmed in the weak page based on the parity data associated with the weak page and the data programmed in the pages adjacent to the weak page,
wherein the parity data is generated by performing an exclusive-OR (XOR) operation on data programmed in the weak page and data programmed in an (i−1)-th page.
13. The method of claim 12 , wherein the parity data and the data programmed in the pages adjacent to the weak page are obtained by controlling the semiconductor memory device to read the parity data and read the data programmed in the pages adjacent to the weak page.
14. The method of claim 12 , wherein:
the page adjacent to the weak page is the (i−1)-th page when the weak page is the i-th page, and
the data programmed in the weak page is recovered by performing an exclusive-OR (XOR) operation on the data programmed in the page adjacent to the weak page and the parity data.
15. The method of claim 12 , wherein:
the pages adjacent to the weak page are the (i−1)-th page and an (i+1)-th page when the weak page is the i-th page, and
the data programmed in the weak page is recovered by performing an exclusive-OR (XOR) operation on the data programmed in the pages adjacent to the weak page and the parity data.
16. The method of claim 12 , further comprising controlling the semiconductor memory device to read the data programmed in the weak page again when the recovering is failed.
17. The method of claim 16 , wherein the semiconductor memory device is controlled to read the data programmed in the weak page again by changing a read voltage.
18. A memory system comprising:
a semiconductor memory device including a plurality of pages; and
a memory controller configured to control the semiconductor memory device,
wherein the memory controller comprises:
a processing unit configured to:
generate a command for controlling a program operation or a read operation of the semiconductor memory device;
generate parity data corresponding to an i-th page which is a weak page among the plurality of pages; and
recover data programmed in the weak page based on the parity data, and
a data storage configured to store the parity data,
wherein the processing unit generates the parity data by performing an exclusive-OR (XOR) operation on data programmed in the weak page and data programmed in an (i−1)-th page.
19. The memory system of claim 18 , wherein the processing unit generates the parity data by performing an exclusive-OR (XOR) operation on the data programmed in the weak page, the data programmed in the (i−1)-th page and data programmed in an (i+1)-th page.