IP Library › Granted Patent US 12,387,024
Granted Patent B2
US 12,387,024 · App. 17/923,674 · Granted Aug 12, 2025

System, method, computer-accessible medium, and circuit for crippling the oracle in logic locking

Inventor: Ozgur Sinanoglu (Abu Dhabi, AE)
Assignee: New York University in Abu Dhabi Corporation
G06F30/337G06F30/30G06F21/00
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,387,024
App. No.
17/923,674
Granted
Aug 12, 2025
Kind
B2
Abstract

Exemplary system, method, and computer-accessible medium for protecting at least one logic-locked integrated circuit (IC) design can include, for example, receiving a request(s), and swapping a correct key which is configured to unlock the logic-locked IC design(s) with an incorrect key which is configured to corrupt an output(s) of the logic-locked IC design(s) after receipt of the request(s). The request(s) can be a test access request(s). The correct key can be utilized when the logic-locked IC design(s) can be initially powered on. The correct key can be swapped with the incorrect key using multiplexer(s) or register(s). In addition, exemplary system, method, and computer-accessible medium can be provided for logic-locking a logic design by, randomly replacing randomly-selected inverters in the logic design with XOR or XNOR key-gates, and inserting XOR or XNOR key-gates randomly in randomly-selected locations in the logic design where there is no inverter.

Claims (29)

1. A non-transitory computer-accessible medium having stored thereon computer-executable instructions for providing at least one logic-locked integrated circuit (IC) design, wherein, when a computing arrangement executes the instructions, the computing arrangement is configured to perform procedures comprising:

randomly selecting at least one first location at a first portion in a logic design which includes first inverters;

randomly selecting at least one second location at a second portion in the logic design which excludes at least one second inverter;

randomly partitioning the at least one first location into at least two first sets, and the at least one second location into at least two second sets;

replacing at least first one of the first inverters in at least first one of the first sets with at least one XOR key-gate;

replacing at least second one of the first inverters in at least second one of the first sets with at least one XNOR key-gate;

inserting the at least one XNOR key-gate in at least first one of the second sets; and

inserting the at least one XOR key-gate in at least second one of the second sets.

2. The computer-accessible medium of claim 1 , wherein:

at least one first input of the at least one XOR key-gate or at least one first input of the at least one XNOR key-gate is driven by a net in the logic design, and

at least one second input of the at least one XOR key-gate or at least one second input of the at least one XNOR key-gate is driven by logic locking key bits, thereby providing the at least one logic-locked IC design.

3. The computer-accessible medium of claim 2 , wherein the logic locking key bits include (i) a correct key which is configured to unlock at least one logic-locked IC design and (ii) an incorrect key which is configured to corrupt at least one output of the at least one logic-locked IC design.

4. A method for providing at least one logic-locked integrated circuit (IC) design, comprising:

randomly selecting at least one first location at a first portion in a logic design which includes first inverters;

randomly selecting at least one second location at a second portion in the logic design which excludes at least one second inverter;

randomly partitioning the at least one first location into at least two first sets, and the at least one second location into at least two second sets;

replacing at least first one of the first inverters in at least first one of the first sets with at least one XOR key-gate;

replacing at least second one of the first inverters in at least second one of the first sets with at least one XNOR key-gate;

inserting the at least one XNOR key-gate in at least first one of the second sets; and

inserting the at least one XOR key-gate in at least second one of the second sets.

5. A system for providing at least one logic-locked integrated circuit (IC) design, comprising:

a computer hardware arrangement configured to:

randomly select at least one first location at a first portion in a logic design which includes first inverters;

randomly select at least one second location at a second portion in the logic design which excludes at least one second inverter;

randomly partition the at least one first location into at least two first sets, and the at least one second location into at least two second sets;

replace at least first one of the first inverters in at least first one of the first sets with at least one XOR key-gate;

replace at least second one of the first inverters in at least second one of the first sets with at least one XNOR key-gate;

insert the at least one XNOR key-gate in at least first one of the second sets; and

insert the at least one XOR key-gate in at least second one of the second sets.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 10, 2023
From: SINANOGLU, OZGUR
To: NEW YORK UNIVERSITY IN ABU DHABI CORPORATION
Reel/Frame 064547/0786 →
Continuity (2)
Provisional Application 63021374 · May 7, 2020
Related Publication 20230177245A1 · Jun 8, 2023
References Cited (42)
US 10153769B2 · Sinanoglu · 2018 [cited by examiner]
US 11657127B2 · Bhunia · 2023 [cited by examiner]
US 20100284539A1 · Roy et al. · 2010 [cited by applicant]
US 20190258766A1 · Wang · 2019 [cited by examiner]
US 20200065456A1 · Tehranipoor et al. · 2020 [cited by applicant]
CN 110020558A · 2019 [cited by applicant]
WO 2018057525A1 · 2018 [cited by applicant]
WO 2019178255A1 · 2019 [cited by applicant]
G. Karypis et al., “Multilevel Hypergraph Partitioning: Applications in VLSI Domain,” IEEE trans. on Very Large Scale Integration (VLSI) Systems, vol. 7, No. 1, Mar. 1999, pp. 69-79. (Year: 1999). [cited by examiner]
Y.-W. Lee et al., “Improving Logic Obfuscation via Logic Cone Analysis,” 2015 16th Latin-American Test Symposium (LATS), 6 pages. (Year: 2015). [cited by examiner]
M. Yasin, et al., “A Brief History of Logic Locking,” Cham: Springer International Publishing, 2020, pp. 17-31. [cited by applicant]
J. Rajendran, et al., “Security analysis of logic obfuscation,” in Proc. 49th Annu. Design Automation Conf (DAC), Jun. 2012, pp. 83-89. [cited by applicant]
“Intel's 22-nm trigate transistors exposed,” 2012. [Online]. Available: http://electroiq.com/chipworks- real- chips-blog/2012/04/24/intels-22-nm-trigate-transistors-exposed. [cited by applicant]
“iPhone 5 A6 SoC reverse engineered, reveals rare hand-made custom CPU, and tri-core GPU,” 2012. [Online]. Available: http: //www.extremetech.com/computing/136749-iphone-5-a6-soc- reverseengineered- reveals-rare-hand-ma… [cited by applicant]
R. Karmakar et al., “Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits,” arXiv preprint arXiv:1801.04961, 2018. [cited by applicant]
U. Guin et al., “Robust design-for-security architecture for enabling trust in IC manufacturing and test,” TVLSI, vol. 26, No. 5, pp. 818-830, 2018. [cited by applicant]
X. Wang et al., “Secure scan and test using obfuscation throughout supply chain,” TCAD, vol. 37, No. 9, pp. 1867-1880, 2017. [cited by applicant]
R. Karmakar et al., “A Scan Obfuscation Guided Design-for-Security Approach For Sequential Circuits,” TCAS II: Express Briefs, 2019. [cited by applicant]
L. Alrahis et al., “ScanSAT: Unlocking Static and Dynamic Scan Obfuscation,” TETC, pp. 1-1, 2019. [cited by applicant]
M. Yasin et al., “On improving the security of logic locking,” TCAD, vol. 35, No. 9, pp. 1411-1424, 2016. [cited by applicant]
P. Subramanyan et al., “Evaluating the security of logic encryption algorithms,” in HOST. IEEE, 2015, pp. 137-143. [cited by applicant]
K. Shamsi et al., “AppSAT: Approximately deobfuscating integrated circuits,” in HOST. IEEE, 2017, pp. 95-100. [cited by applicant]
Y. Shen and H. Zhou, “Double DIP: Re-evaluating security of logic encryption algorithms,” in GLSVLSI. ACM, 2017, pp. 179-184. [cited by applicant]
X. Xu et al., “Novel bypass attack and BDD-based tradeoff analysis against all known logic locking attacks,” in CHES. Springer, 2017, pp. 189-210. [cited by applicant]
D. Sirone and P. Subramanyan, “Functional analysis attacks on logic locking,” in DATE. IEEE, 2019, pp. 936-939. [cited by applicant]
M. El Massad et al., “Reverse engineering camouflaged sequential circuits without scan access,” in ICCAD. IEEE/ACM, 2017, pp. 33-40. [cited by applicant]
M. Yasin et al., “Removal Attacks on Logic Locking and Camouflaging Techniques,” TETC, pp. 1-1, 2017. [cited by applicant]
F. Yang et al., “Stripped Functionality Logic Locking With Hamming Distance-Based Restore Unit (SFLL-hd)-Unlocked,” TIFS, vol. 14, No. 10, pp. 2778-2786, 2019. [cited by applicant]
M. Yasin et al., “SARLock: SAT attack resistant logic locking,” in HOST. IEEE, 2016, pp. 236-241. [cited by applicant]
Y. Xie and A. Srivastava, “Anti-sat: Mitigating sat attack on logic locking,” TCAD, vol. 38, No. 2, pp. 199-207, 2019. [cited by applicant]
M. Yasin et al., “Provably-secure logic locking: From theory to practice,” in CCS. ACM, 2017, pp. 1601-1618. [cited by applicant]
J. Roy et al., “Ending Piracy of Integrated Circuits,” Computer, vol. 43, No. 10, pp. 30-38, 2010, submitted as DATE08, 2008 EDAA. [cited by applicant]
J. Rajendran et al., “Fault analysis-based logic encryption,” TCOMP, vol. 64, No. 2, pp. 410-424, 2015. [cited by applicant]
A. Sengupta, M. Nabeel, N. Limaye, M. Ashraf, and O. Sinanoglu, “Truly stripping functionality for logic locking: A fault-based perspective,” IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., pp. 1-1, 2020. [cited by applicant]
M. Yasin et al., “Activation of logic encrypted chips: Pre-test or posttest?” in DATE. EDA Consortium, 2016, pp. 139-144. [cited by applicant]
Written Opinion and Search Report for International Patent Application No. PCT/IB2021/053917 mailed on Jul. 27, 2021. [cited by applicant]
Rajit Karmakar et al. “Encrypt Flip-Flop: A Novel Logic Encryption Technique For Sequential Circuits,” Jan. 2018 [retrieved from internet on Jul. 21, 2021], <URL: https://arxiv.org/pdf/1801.04961.pdf>. [cited by applicant]
Knechtel, J. et al., “Protect Your Chip Design Intellectual Property: An Overview”, Proceedings of the International Conference on Omni-Layer Intelligent Systems (COINS'I 9), May 2019, pp. 211-216. [cited by applicant]
Shamsi, K. et al., “On the Approximation Resiliency of Logic Locking and IC Camouflaging Schemes”, IEEE Transactions on Information Forensics and Security, vol. 14, No. 2, Feb. 2019. [cited by applicant]
United Arab Emirates Ministry of Economy, Office Action issued in Application No. P6002311/2022 dated Dec. 13, 2024, 8 pages. [cited by applicant]
United Arab Emirates Ministry of Economy, Search report issued in Application No. P6002311/2022 dated Dec. 13, 2024, 3 pages. [cited by applicant]
Notification Concerning Transmittal of International Preliminary Report on Patentability (Chapter I of the Patent Cooperation Treaty) dated Nov. 17, 2022 for International Patent Application No. PCT/IB2021/053917. [cited by applicant]