Orthogonal printed circuit board interface
A dual-polarized PCB array antenna includes one or more PCBs and a radiating antenna array. Each PCB has a PCB mounting surface that extends from a first PCB end to an opposing second PCB end. The radiating antenna array includes one or more radiator substrates. Each radiator substrate has a patch mounting surface that extends from a first substrate end to an opposing second substrate end. The dual-polarized PCB array antenna further includes one or more orthogonal interfaces configured to arrange the patch mounting surface of a given radiator substrates in an orthogonal position with respect to the PCB mounting surface of a given PCB.
1. A shielded channel interface included in a dual-polarized printed circuit board (PCB) array antenna, the shielded channel interface comprising:
a plurality of first electrically conductive elements coupled to a PCB mounting surface of a PCB;
a plurality of second electrically conductive elements coupled to a patch mounting surface of a radiator substrate, the plurality of second electrically conductive elements extending perpendicular from the patch mounting surface to establish electrical connections to the plurality of first electrically conductive elements,
wherein at least two first connections among the electrical connections are configured to receive a first signal and at least one second connection among the electrical connections is configured to receive a second signal different from the first signal, the at least one second connection interposed between the at least two first connections.
2. The shielded channel interface of claim 1 , wherein the electrical connections establish a ground-signal-ground configuration.
3. The shielded channel interface of claim 1 , wherein the electrical connections establish a signal-ground-signal configuration.
4. The shielded channel interface of claim 1 , wherein the plurality of first electrically conductive elements include at least one electrically conductive trace formed on the PCB mounting surface.
5. The shielded channel interface of claim 4 , wherein each of the at least one electrically conductive trace includes a first end in signal communication with a port and a second end in signal communication with a ground plane.
6. The shielded channel interface of claim 5 , wherein the plurality of second electrically conductive elements include at least one electrically conductive pin.
7. The shielded channel interface of claim 6 , wherein the at least one electrically conductive pin is connected to the at least one electrically conductive trace.