Granted Patent B2

US 12,389,295 · App. 17/561,897 · Granted Aug 12, 2025

Inventors: Jing Zhu (Portland, OR); Menglei Zhang (Portland, OR); Juan Fang (Portland, OR); Shu-ping Yeh (Campbell, CA); Shilpa Talwar (Cupertino, CA); Valerie Parker (Portland, OR)

Assignee: Intel Corporation

H04W36/22H04W28/0236H04W36/0066

Abstract

Claims (41)

1. A multi-access (MX) compute node to operate in an MX computing environment, the MX compute node comprising:

memory circuitry; and

processor circuitry connected to the memory circuitry, the processor circuitry to execute instructions for traffic steering, which, when executed are to cause the processor circuitry to:

initiate establishment of a set of logical links with another MX compute node, wherein each logical link of the set of logical links includes a respective set of physical links,

select a logical link of the set of logical links over which to steer traffic,

select a physical link of a set of physical links belonging to the selected logical link over which to steer traffic,

cause a traffic-steering message (TSM) to be sent to the other MX compute node over the selected physical link,

receive a traffic-steering acknowledgement (TSA) from the other MX compute node over the selected physical link,

receive traffic from the other MX compute node over the selected physical link, and

steer second traffic to be sent to the other MX compute node over the second physical link and from being sent to the other MX compute node over the selected physical link or one or more other links of the set of physical links.

2. The MX compute node of claim 1 , wherein the selected physical link is a first physical link, the TSM is a first TSM, the TSA is a first TSA, the received traffic is first traffic, and execution of the instructions is to cause the processor circuitry to:

receive a second TSM from the other MX compute node over a second physical link of the plurality of physical links; and

send a second TSA to the other MX compute node over the second physical link.

3. The MX compute node of claim 2 , wherein execution of the instructions is to cause the processor circuitry to:

detect link quality degradation of the first physical link;

select a third link of the plurality of physical links over which to steer traffic based on the detected link quality degradation;

send a third TSM to the other MX compute node over the third link;

receive a third TSA from the other MX compute node over the third link; and

receive third traffic from the other MX compute node over the third link.

4. The MX compute node of claim 2 , further comprising:

first transceiver (TRx) circuitry connected to the processor circuitry, the first TRx circuitry configured to operate according to a first radio access technology (RAT), and the first TRx to:

transmit the first TSM over the first physical link,

receive the first TSA over the first physical link, and

receive the first traffic from the other MX compute node over the selected; and

second TRx circuitry connected to the processor circuitry, the second TRx circuitry configured to operate according to a second RAT, and the second TRx circuitry to:

receive the second TRS over the second physical link,

send the second TSA over the second physical link, and

send the second traffic over the second physical link.

5. The MX compute node of claim 2 , wherein the first RAT is different than the second RAT.

6. The MX compute node of claim 1 , wherein execution of the instructions is to cause the processor circuitry to:

cause, on a periodic basis, a probe message to be sent over non-active links of the plurality of physical links to maintain the non-active links.

7. The MX compute node of claim 1 , wherein execution of the instructions is to cause the processor circuitry to:

cause retransmission of the TSM to the other MX compute node when the TSA is not received before a TSM timeout (TO) timer expires.

8. The MX compute node of claim 1 , wherein execution of the instructions is to cause the processor circuitry to:

select the selected physical link among the plurality of physical links based on one or more quality of service (QOS) measurements of individual links of the plurality of physical links.

9. The MX compute node of claim 1 , wherein each logical link of the set of logical links has a connection identifier (ID), and each physical link of the respective set of physical links has a same connection ID as a corresponding one of the set of logical links.

10. The MX compute node of claim 9 , wherein at least one logical link of the set of logical links operates according to a radio access technology (RAT) different than RATs of other logical links of the plurality of links.

11. The MX compute node of claim 9 , wherein at least one physical link of at least one set of physical links belonging to at least one logical link of the set of logical links belongs to a RAT different from a RAT of other physical links in the at least one set of physical links.

12. The MX compute node of claim 1 , wherein:

the TSM is a Multi-Access Management Services (MAMS) traffic-steering request message, a MAMS traffic-steering response message, a MAMS probe request message, or a MAMS traffic-splitting update (TSU) message; and

the TSA is a MAMS traffic-steering request message, a MAMS traffic-steering response message, a MAMS probe acknowledgement message, or a MAMS traffic-splitting acknowledgement (TSA) message.

Assignments (1)

Continuity (1)

References Cited (165)

Cited By (1)

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