Semiconductor structure and method for manufacturing same
A method for manufacturing a semiconductor structure includes: providing a substrate; forming a gate trench in the substrate, the gate trench including a first trench and a second trench, the second trench being located above the first trench, communicating with the first trench, and having a width greater than a width of the first trench; and forming a gate word line in the gate trench.
1. A method for manufacturing a semiconductor structure, comprising:
providing a substrate;
forming a gate trench in the substrate, the gate trench including a first trench and a second trench, the second trench being located above the first trench, communicating with the first trench, having a width greater than a width of the first trench; and
forming a gate word line in the gate trench;
wherein
the forming the gate trench in the substrate comprises:
forming the first trench in the substrate;
forming a sacrificial layer, wherein the sacrificial layer comprises a first part and a second part, the first trench is filled up by the first part, and the second part covers an upper surface of the substrate and an upper surface of the first part;
forming an isolation groove in the second part to form a sacrificial pattern by patterning the second part, wherein the sacrificial pattern is arranged to correspond to the first part, and has a width greater than a width of the first part;
forming a filling layer in the isolation groove, wherein the isolation groove is filled up by with the filling layer;
removing the sacrificial pattern to form the second trench; and
removing the first part;
wherein
the filling layer comprises a silicon layer or a germanium layer or a silicon germanium layer grown by an epitaxial method.
2. The method for manufacturing the semiconductor structure of claim 1 , further comprising:
subjecting the filling layer with thermal treatment to form a second oxide layer on a surface of the filling layer.
3. The method for manufacturing the semiconductor structure of claim 2 , further comprising:
forming a first oxide layer on a side wall of the first trench, wherein the first oxide layer and the second oxide layer are seamlessly connected on a surface of the gate trench.
4. The method for manufacturing the semiconductor structure of claim 3 , wherein
the forming the gate word line in the gate trench comprises:
forming a word line conductive layer in the gate trench, wherein the first trench is filled up by the word line conductive layer which extends into the second trench.
5. The method for manufacturing the semiconductor structure of claim 1 , wherein
the substrate comprises an array region and an edge region located at a periphery of the array region; the gate word line is located in the array region and the edge region;
the method further comprising: after forming the gate word line, forming a top dielectric layer on the substrate, wherein the top dielectric layer covers the array region and the edge region;
forming a first interconnection structure in the top dielectric layer on the edge region, wherein the first interconnection structure penetrates through the top dielectric layer, and electrically connects with the word line conductive layer.
6. The method for manufacturing the semiconductor structure of claim 5 , wherein
the substrate comprises an active area and an isolation structure;
the gate word line in the edge region is located in the isolation structure.
7. The method for manufacturing the semiconductor structure of claim 6 , further comprising:
forming a functional device and a lead-out bonding pad electrically connected to the functional device in the edge region, prior to the forming the top dielectric layer on the substrate; wherein an upper surface of the word line conductive layer is located lower than the upper surface of the second trench;
forming an auxiliary conductive layer on the upper surface of the word line conductive layer, after the forming the word line conductive layer; wherein an upper surface of the auxiliary conductive layer is flush with an upper surface of the lead-out bonding pad, and the first interconnection structure is connected to the auxiliary conductive layer.