Combined memory module logic devices for reduced cost and improved functionality
An apparatus, comprising a plurality of memories and a single integrated circuit (IC) that is configured to be coupled to a host device by a host bus and that is coupled to the plurality of memories by a memory bus, wherein the IC comprises a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the plurality of memories, and a power management integrated circuit (PMIC) module that is configured to regulate voltage and monitor current provided to the plurality of memories.
1. An apparatus, comprising:
a plurality of memories; and
a single integrated circuit (IC) that is configured to be coupled to a host device by a host bus and that is coupled to the plurality of memories by a memory bus, wherein the IC comprises:
a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the plurality of memories and to monitor a status of the plurality of memories, and
a power management integrated circuit (PMIC) module that is coupled with the logic buffer module, wherein the PMIC is configured, based on the monitored status of the plurality of memories, to enable a dynamic supply voltage scaling for the plurality of memories.
2. The apparatus of claim 1 , wherein the plurality of memories comprises double data rate synchronous dynamic random-access memories.
3. The apparatus of claim 1 , wherein the PMIC module is further configured to enable threshold voltage protection, programmable power on sequence, or power management to the plurality of memories.
4. The apparatus of claim 1 , wherein the PMIC module is further configured to regulate voltage and monitor current provided to the plurality of memories.
5. The apparatus of claim 1 , wherein the single IC further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the plurality of memories.
6. The apparatus of claim 1 , wherein the single IC further comprises a temperature control module.
7. The apparatus of claim 1 , wherein the single IC further comprises a security logic module.
8. The apparatus of claim 1 , wherein the single IC is configured to support multi-level signaling between the host device and the plurality of memories.
9. The apparatus of claim 1 , wherein the single IC is configured to support various buffering operations including Fist-In-First-Out (FIFO), Last-In-First-Out (LIFO), or out-of-order execution.
10. The apparatus of claim 1 , wherein the logic buffer of the single IC permits configurability of memory bus width and clock speed.
11. A memory system, comprising:
a host device;
a memory module including:
a first plurality of memory devices, and
a first single integrated circuit (IC) coupled to the first plurality of memory devices by a first memory bus, wherein the first single IC comprises:
a first logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the first plurality of memory devices and to monitor a status of the first plurality of memories, and
a first power management integrated circuit (PMIC) module that is coupled with the first logic buffer module, wherein the first PMIC is configured, based on the monitored status of the first plurality of memory devices, to enable a first dynamic supply voltage scaling for the first plurality of memory devices; and
a host bus that is configured to couple the host device and the memory module.
12. The memory system of claim 11 , wherein the memory module further comprises:
a second plurality of memory devices, and
a second single IC coupled to the second plurality of memory devices by a second memory bus, wherein the second single IC comprises:
a second logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between the host device and the second plurality of memory devices and to monitor a status of the second plurality of memories, and
a second PMIC module that is coupled with the second logic buffer module, wherein the second PMIC is configured, based on the monitored status of the second plurality of memory devices, to enable a second dynamic supply voltage scaling for the second plurality of memory devices.
13. The memory system of claim 12 , wherein each of the first and second single ICs further comprises a temperature control module.
14. The memory system of claim 12 , wherein each of the first and second single ICs further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the memory module.
15. The memory system of claim 12 , wherein each of the first and second single ICs further comprises a security logic module.
16. The memory system of claim 12 , wherein the PMIC module of each of the first and second single ICs is configured to enable threshold voltage protection, programmable power on sequence, or power management to the first and second plurality of memory devices, respectively.
17. The memory system of claim 11 , wherein the memory module comprises double data rate synchronous dynamic random-access memories.
18. An integrated circuit (IC), comprising:
a logic buffer module that is configured to buffer data signals, command signals, address signals, and clock signals between a host device and one or more corresponding memory channels of a memory module and to monitor a status of the memory module;
a power management integrated circuit (PMIC) module that is coupled with the logic buffer module, wherein the PMIC is configured, based on the monitored status of the memory module, to enable a dynamic supply voltage scaling for the memory module;
memory bus terminals that are configured to be coupled to the one or more memory channels; and
host bus terminals that are configured to be coupled to the host device.
19. The integrated circuit of claim 18 , further comprises a serial presence detect (SPD) hub that is configured to control plane communication between components of the IC and the host device, and to decouple load from the host device to the corresponding one or more memory channels of the memory module.
20. The integrated circuit of claim 18 , further comprising a temperature control module and a security logic module.