Methods and apparatus to facilitate write miss caching in cache system
Methods, apparatus, systems and articles of manufacture to facilitate write miss caching in cache system are disclosed. An example apparatus includes a first cache storage; a second cache storage, wherein the second cache storage includes a first portion operable to store a first set of data evicted from the first cache storage and a second portion; a cache controller coupled to the first cache storage and the second cache storage and operable to: receive a write operation; determine that the write operation produces a miss in the first cache storage; and in response to the miss in the first cache storage, provide write miss information associated with the write operation to the second cache storage for storing in the second portion.
1. A device comprising:
a cache memory; and
a cache controller coupled to the cache memory and configured to:
allocate a portion of the cache memory as a write miss cache;
receive a write operation;
determine whether the write operation is associated with a miss in a remainder of the cache memory;
based on the write operation being associated with the miss in the remainder of the cache memory, cause a set of write miss information to be stored in the write miss cache;
receive a read operation that is associated with the write operation; and
service the read operation using the set of write miss information stored in the write miss cache.
2. The device of claim 1 , wherein:
the set of write miss information includes a set of data associated with the write operation; and
the servicing of the read operation includes providing the set of data from the write miss cache.
3. The device of claim 1 , wherein:
the cache memory is a first cache memory;
the device further comprises a second cache memory coupled to the cache controller and configured to be a main cache; and
the cache controller is configured to:
allocate the remainder of the cache memory as a victim cache; and
cause the set of write miss information to be stored in the write miss cache further based on the write operation being associated with a miss in the main cache.
4. The device of claim 3 , wherein:
the main cache is a level-one (L1) main cache;
the victim cache is an L1 victim cache; and
the cache controller is an L1 cache controller.
5. The device of claim 4 , wherein the cache controller is configured to:
compare a utilization of the write miss cache to a threshold; and
based on the utilization exceeding the threshold, cause the set of write miss information to be provides to a level-two (L2) cache subsystem.
6. The device of claim 5 , wherein the threshold corresponds to a bandwidth of an interface of the L2 cache subsystem.
7. The device of claim 5 , wherein the threshold corresponds to a size of the write miss cache.
8. The device of claim 1 , wherein:
the set of write miss information is a first set of write miss information; and
the cache controller is configured to, when a first memory address of the first set of write miss information corresponds to a second memory address of a second set of write miss information stored in the write miss cache, to merge the first set of write miss information with the second set of write miss information.
9. The device of claim 1 , wherein the write miss cache includes a byte enable register.
10. The device of claim 9 , wherein the byte enable register is configured to store a value that specifies an element of the set of write miss information to be written.
11. A device comprising:
a processing core configured to provide a write operation;
a cache controller coupled to the processing core;
a first cache memory coupled to the processing core; and
a second cache memory coupled to the processing core that includes a write miss cache and a remainder;
wherein the cache controller is configured to:
determine whether the write operation is associated with a miss in the first cache memory and a miss in the remainder of the second cache memory;
based on the write operation being associated with the miss in the first cache memory and the miss in the remainder of the second cache memory, cause a set of write miss information to be stored in the write miss cache;
receive a read operation that is associated with the write operation; and
service the read operation using the set of write miss information stored in the write miss cache.
12. A method comprising:
allocating a portion of a cache memory as a write miss cache;
receiving a write operation;
determining whether the write operation is associated with a miss in a remainder of the cache memory;
based on the write operation being associated with the miss in the remainder of the cache memory, storing a set of write miss information in the write miss cache;
receiving a read operation that is associated with the write operation; and
servicing the read operation using the set of write miss information stored in the write miss cache.
13. The method of claim 12 , wherein:
the set of write miss information includes a set of data associated with the write operation; and
servicing the read operation using the set of write miss information comprises providing the set of data from the write miss cache.
14. The method of claim 12 , wherein:
the cache memory is a first cache memory; and
the method further comprises:
allocating the remainder of the first cache memory as a victim cache; and
storing the set of write miss information in the write miss cache further based on the write operation being associated with a miss in a second cache memory.
15. The method of claim 14 , wherein:
the second cache memory is a level-one (L1) main cache; and
the first cache memory is an L1 victim cache.
16. The method of claim 15 , further comprising:
comparing a utilization of the write miss cache to a threshold; and
based on the utilization exceeding the threshold, providing the set of write miss information to a level-two (L2) cache subsystem.
17. The method of claim 16 , wherein the threshold corresponds to a bandwidth of an interface of the L2 cache subsystem.
18. The method of claim 16 , wherein the threshold corresponds to a size of the write miss cache.
19. The method of claim 12 , wherein:
the set of write miss information is a first set of write miss information; and
the method further comprises, when a first memory address of the first set of write miss information corresponds to a second memory address of a second set of write miss information stored in the write miss cache, merging the first set of write miss information with the second set of write miss information.
20. The method of claim 12 , wherein:
the write miss cache includes a byte enable register; and
the method further comprises storing a value in the byte enable register that specifies an element of the set of write miss information to be written.