IP Library › Granted Patent US 12,394,016
Granted Patent B2
US 12,394,016 · App. 17/907,845 · Granted Aug 19, 2025

Low delay super-resolution processing

Inventor: Katsushi Otsuka (Tokyo, JP)
Assignee: Sony Interactive Entertainment Inc.
G06T3/4053H04N19/172
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,394,016
App. No.
17/907,845
Granted
Aug 19, 2025
Kind
B2
Abstract

A client terminal includes a data acquiring section, a super-resolution processing section 48 , and a display control section. The data acquiring section of the client terminal acquires video data in units of partial image which is smaller than one frame. The super-resolution processing section of the client terminal executes a super-resolution process in units of partial image acquired by the data acquiring section. The display control section of the client terminal sequentially outputs, to a display panel, partial images having undergone the super-resolution process at the super-resolution processing section.

Claims (21)

1. An image processing apparatus comprising:

one or more processors; and

one or more memories storing instruction that, when executed by the one or more processors, cause the image processing apparatus to perform operations comprising:

acquiring video data in units of partial image which is smaller than one frame;

executing a super-resolution process in the units of partial image, wherein executing the super-resolution process comprises acquiring first scene information prior to compression-encoding a unit of partial image of the units of partial image and acquiring second scene information after compression-encoding the unit of partial image, wherein the second scene information is generated based on a compression-encoded partial image, wherein executing the super-resolution process comprises switching a model for the super-resolution process based on the first scene information and the second scene information; and

sequentially outputting, to a display section, partial images that have undergone the super-resolution process.

2. The image processing apparatus according to claim 1 , the operations further comprising:

expansion-decoding a compression-encoded partial image to form an expansion-decoded partial image, and

executing a super-resolution process on the expansion-decoded partial image.

3. The image processing apparatus according to claim 1 , wherein executing the super-resolution process comprises performing a scene analysis on a basis of a partial image, and executing the super-resolution process for the partial image on a basis of a result of the scene analysis.

4. The image processing apparatus according to claim 3 , wherein executing the super-resolution process comprises generating one or more partial images, each partial image of the one or more partial images having a resolution which is lower than a resolution of a partial image, and performing a scene analysis of the one or more partial images in order from a partial image with a relatively low resolution to a partial image with a relatively high resolution.

5. The image processing apparatus according to claim 3 , wherein executing the super-resolution process comprises extracting, from discrete positions in the partial image, a plurality of region images of an analysis unit granularity that is smaller than a partial image, and performing the scene analysis based on the plurality of region images.

6. The image processing apparatus according to claim 3 , wherein executing the super-resolution process comprises performing the scene analysis by referring to internal drawing data held in an application, before the application generates a final drawing result, and uses a result of the scene analysis for the super-resolution process.

7. The image processing apparatus according to claim 1 , wherein executing the super-resolution process comprises referring to internal drawing data held in an application, before the application generates a final drawing result, and uses the internal drawing data for the super-resolution process.

8. The image processing apparatus according to claim 1 , wherein executing the super-resolution process comprises selecting simplification or nonexecution of the super-resolution process on a basis of scene information that indicates a feature in a partial image acquired as a result of a process prior to executing the super-resolution process.

9. The image processing apparatus according to claim 1 , wherein the second scene information is acquired before the compression-encoded partial image is expansion-decoded.

10. The image processing apparatus according to claim 1 , wherein executing the super-resolution process comprises acquiring scene information by using internal drawing data held in an application, before the application generates a final drawing result, and switching a model for the super-resolution process on a basis of the scene information.

11. The image processing apparatus according to claim 1 , wherein executing the super-resolution process comprises dividing a partial image into Y-component data and UV-component data, and does not execute a super-resolution process for the UV-component data but executes a super-resolution process for the Y-component data.

12. The image processing apparatus according to claim 11 , wherein

a common identification is given to the Y-component data and the UV-component data that are originated from a same partial image, and

the UV-component data is buffered during the super-resolution process for the Y-component data, and is combined with the Y-component data with the common identification, the Y-component data having been undergone the super-resolution process.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 29, 2022
From: OTSUKA, KATSUSHI
To: SONY INTERACTIVE ENTERTAINMENT INC.
Reel/Frame 060930/0066 →
Priority Claims (1)
JP 2020-054671 · Mar 25, 2020 · national
Continuity (1)
Related Publication 20230128106A1 · Apr 27, 2023
References Cited (35)
US 5742710A · Hsu · 1998 [cited by applicant]
US 8531736B2 · Matsunaga · 2013 [cited by applicant]
US 9697583B2 · Motohashi · 2017 [cited by applicant]
US 10225624B2 · Long · 2019 [cited by applicant]
US 12112451B2 · Otsuka · 2024 [cited by examiner]
US 20050019000A1 · In-Keon · 2005 [cited by applicant]
US 20070115371A1 · Enomoto · 2007 [cited by applicant]
US 20070139536A1 · Watanabe · 2007 [cited by applicant]
US 20100026885A1 · Terada · 2010 [cited by applicant]
US 20100073732A1 · Matsunaga · 2010 [cited by applicant]
US 20100119157A1 · Kameyama · 2010 [cited by examiner]
US 20120147205A1 · Lelescu · 2012 [cited by examiner]
US 20150003528A1 · Toichi · 2015 [cited by applicant]
US 20150332435A1 · Motohashi · 2015 [cited by applicant]
US 20160330531A1 · Long · 2016 [cited by examiner]
US 20190052883A1 · Ikeda · 2019 [cited by applicant]
US 20210066373A1 · Toda · 2021 [cited by applicant]
US 20210097646A1 · Choi · 2021 [cited by examiner]
JP 7262381A · 1995 [cited by applicant]
JP 2005020761A · 2005 [cited by applicant]
JP 2007148537A · 2007 [cited by applicant]
JP 2009117886A · 2009 [cited by applicant]
JP 2009296208A · 2009 [cited by applicant]
JP 2010074732A · 2010 [cited by applicant]
JP 2010278898A · 2010 [cited by applicant]
JP 2012049747A · 2012 [cited by applicant]
JP 2013127718A · 2013 [cited by applicant]
JP 2013128286A · 2013 [cited by applicant]
JP 2015012548A · 2015 [cited by applicant]
JP 2015232869A · 2015 [cited by applicant]
JP 2016054459A · 2016 [cited by applicant]
JP 2017510114A · 2017 [cited by applicant]
JP 2019129328A · 2019 [cited by applicant]
International Search Report for corresponding PCT Application No. PCT/JP2021/012026, 6 pages, dated Jun. 22, 2021. [cited by applicant]
International Search Report for related PCT Application No. PCT/JP2021/012027, 6 pages, dated Jun. 29, 2021. [cited by applicant]