IP Library › Granted Patent US 12,394,343
Granted Patent B2
US 12,394,343 · App. 18/399,338 · Granted Aug 19, 2025

Display device

Inventors: Jaekyung Choi (Goyang-si, KR); Junhyuk Song (Seoul, KR)
Assignee: LG Display Co., Ltd.
G09G3/035G09G3/32H10H29/142G09G2300/0426G09G2330/021
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Quick Facts
Patent No.
US 12,394,343
App. No.
18/399,338
Granted
Aug 19, 2025
Kind
B2
Abstract

According to an aspect of the present disclosure, a display device includes a lower substrate which is divided into an active area and a non-active area and is stretchable; a plurality of pixels which is disposed on the active area of the lower substrate; a power supply which is disposed on the non-active area of the lower substrate; a plurality of lower connection lines which is disposed on the lower substrate and is connected to each of the plurality of pixels; an upper substrate which is opposite to the lower substrate and is stretchable; a plurality of conductive patterns which is disposed below the upper substrate and is connected to the plurality of pixels, respectively; and a plurality of upper connection lines which is disposed below the upper substrate and is connected to the plurality of conductive patterns. The power supply is electrically connected to the plurality of pixels through a part of the plurality of upper connection lines and a part of the plurality of lower connection lines, to stably supply a voltage to the plurality of pixels.

Claims (57)

1. A display device, comprising:

a lower substrate having an active area and a non-active area, the lower substrate being stretchable;

a plurality of pixels disposed on the active area of the lower substrate;

a power supply disposed on the non-active area of the lower substrate;

a plurality of lower connection lines disposed on the lower substrate and connected to each of the plurality of pixels;

an upper substrate which is spaced from the lower substrate, the upper substrate being stretchable;

a plurality of conductive patterns disposed between the upper substrate and the lower substrate, the plurality of conductive patterns being connected to the plurality of pixels, respectively; and

a plurality of upper connection lines disposed between the upper substrate and the lower substrate, the plurality of upper connection lines being connected to the plurality of conductive patterns, respectively,

wherein the power supply is electrically connected to each of the plurality of pixels through at least one of the plurality of upper connection lines and at least one of the plurality of lower connection lines.

2. The display device according to claim 1 ,

wherein the power supply includes:

a plurality of first power blocks and a plurality of second power blocks disposed on the same layer; and

a plurality of third power blocks which is disposed on a different layer from the plurality of first power blocks and the plurality of second power blocks.

3. The display device according to claim 2 ,

wherein the plurality of first power blocks is disposed inside from the plurality of second power blocks.

4. The display device according to claim 2 ,

wherein the plurality of third power blocks is connected to the plurality of lower connection lines.

5. The display device according to claim 1 ,

wherein each of the plurality of conductive patterns includes:

a plurality of first conductive patterns disposed in the active area; and

a plurality of second conductive patterns disposed in the non-active area.

6. The display device according to claim 5 ,

wherein each of the plurality of first power blocks is connected to each of the plurality of second conductive patterns through a contact hole in a layer between the plurality of first power blocks and the plurality of second conductive patterns and each of the plurality of second power blocks is connected to each of the plurality of third power blocks through a contact hole in a layer between the plurality of second power blocks and the plurality of third power blocks.

7. The display device according to claim 6 ,

wherein a low potential voltage is applied to the plurality of first power blocks and the plurality of second conductive patterns and a high potential voltage is applied to the plurality of second power blocks and the plurality of third power blocks.

8. The display device according to claim 5 ,

wherein each of the plurality of first power blocks is connected to each of the plurality of third power blocks through a contact hole in a layer between the plurality of first power blocks and the plurality of third power blocks and each of the plurality of second power blocks is connected to each of the plurality of second conductive patterns through a contact hole in a layer between the plurality of second power blocks and the plurality of second conductive patterns.

9. The display device according to claim 8 ,

wherein a low potential voltage is applied to the plurality of second power blocks and the plurality of second conductive patterns and a high potential voltage is applied to the plurality of first power blocks and the plurality of third power blocks.

10. The display device according to claim 5 ,

wherein each of the plurality of pixels includes a vertical light emitting diode which is electrically connected to any one of the plurality of first conductive patterns.

11. The display device according to claim 1 ,

wherein only a low potential voltage is applied to the plurality of conductive patterns.

12. The display device according to claim 1 ,

wherein a plurality of lower plate patterns is formed between the lower substrate and the plurality of pixels,

a plurality of lower line patterns is formed between the lower substrate and the plurality of lower connection lines and is connected to the plurality of lower plate patterns, and

a modulus of elasticity of each of the plurality of lower plate patterns and the plurality of lower line patterns is higher than a modulus of elasticity of the lower substrate.

13. The display device according to claim 1 ,

wherein a plurality of upper plate patterns is formed between the upper substrate and the plurality of conductive patterns,

a plurality of upper line patterns is formed between the upper substrate and the plurality of upper connection lines is connected to the plurality of upper plate patterns, and

a modulus of elasticity of each of the plurality of upper plate patterns and the plurality of upper line patterns is higher than a modulus of elasticity of the upper substrate.

14. A display device, comprising:

a lower substrate having an active area and a non-active area, the lower substrate being stretchable;

a plurality of drive transistors disposed on the active area of the lower substrate;

a plurality of switching transistors disposed on the active area of the lower substrate, respective ones of the plurality of switching transistors being connected to respective ones of the drive transistors;

a power supply disposed on the non-active area of the lower substrate;

a plurality of lower connection lines disposed on the lower substrate and connected to respective ones of each of the plurality of switching transistors;

an upper substrate which is spaced from the lower substrate, the upper substrate being stretchable;

a plurality of conductive patterns disposed adjacent to the upper substrate;

a plurality of light emitting diodes (LEDs) electrically connected to respective conductive patterns;

a plurality of upper connection lines disposed between the upper substrate and the LEDs to electrically connect respective ones of the LEDs to the conductive patterns;

wherein the power supply is configured to be electrically connected to each of the plurality of LEDs through the drive transistors based on signals from the switching transistors.

15. The display device of claim 14 wherein the plurality of conductive patterns are between the upper substrate and the lower substrate.

16. The display device of claim 14 wherein a single LED, a single drive transistor and a first plurality of switching transistors are electrically connected to each other to form a single subpixel.

17. The display device of claim 14 further including a plurality of lower plate patterns are disposed on the lower substrate, each lower plate pattern of the plurality having three subpixels thereon to form a single pixel on the lower plate pattern.

18. The display device of claim 17 further including a plurality of inorganic insulating layers over the lower plate pattern, a bank layer over the plurality of inorganic insulation layers and an opening in the bank layer.

19. The display device of claim 18 in which the entire LED is positioned in the opening of the bank layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 4, 2024
From: CHOI, JAEKYUNG; SONG, JUNHYUK
To: LG DISPLAY CO., LTD.
Reel/Frame 066022/0973 →
Priority Claims (1)
KR 10-2022-0190465 · Dec 30, 2022 · national
Continuity (1)
Related Publication 20240221562A1 · Jul 4, 2024
References Cited (9)
US 11538851B2 · Choi et al. · 2022 [cited by applicant]
US 11552152B2 · Shim · 2023 [cited by examiner]
US 20190288234A1 · Kim · 2019 [cited by examiner]
US 20220352252A1 · Lee et al. · 2022 [cited by applicant]
KR 20200017336A · 2020 [cited by examiner]
KR 20200137059A · 2020 [cited by applicant]
TW 202221922A · 2022 [cited by applicant]
TW I767615B · 2022 [cited by applicant]
Translation of KR-20200017336-A (Year: 2020). [cited by examiner]