IP Library › Granted Patent US 12,394,373
Granted Patent B2
US 12,394,373 · App. 17/793,672 · Granted Aug 19, 2025

Pixel driving circuit and display panel

Inventor: Liang Hu (Guangdong, CN)
Assignee: TCL China Star Optoelectronics Technology Co., Ltd.
G09G3/3233G09G3/32G09G2300/0852G09G2320/0233
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Quick Facts
Patent No.
US 12,394,373
App. No.
17/793,672
Granted
Aug 19, 2025
Kind
B2
Abstract

A pixel driving circuit and a display panel are provided. The pixel driving circuit includes a driving transistor connected in series with a light-emitting element between a first power supply line and a second power supply line, a data transistor electrically connected to a gate electrode of the driving transistor, a boost module configured to load a boost input signal. An output terminal of the boost module is electrically connected to the gate electrode of the driving transistor to increase a voltage of the gate electrode of the driving transistor from a first voltage to the second voltage. A connection point between a first capacitor and a second capacitor is connected to the gate electrode of the driving transistor.

Claims (69)

1. A pixel driving circuit, comprising:

a driving transistor connected in series with a light-emitting element between a first power supply line and a second power supply line, wherein a source electrode of the driving transistor is electrically connected to the light-emitting element;

a data transistor, wherein a source electrode of the data transistor is electrically connected to a data line, a drain electrode of the data transistor is electrically connected to a gate electrode of the driving transistor, and a gate electrode of the data transistor is configured to receive a data control signal; and

a boost module, wherein an input terminal of the boost module is configured to receive a boost input signal, and an output terminal of the boost module is electrically connected to the gate electrode of the driving transistor,

wherein in a first stage, the gate electrode of the driving transistor has a first voltage and the driving transistor is turned on to drive the light-emitting element to emit light at a first luminance;

in a second stage after the first stage, the boost module is configured to control a voltage of the gate electrode of the driving transistor to increase from the first voltage to a second voltage greater than the first voltage and the driving transistor is turned on to drive the light-emitting element to emit light at a second luminance greater than the first luminance; and

the boost module comprises:

a first capacitor, wherein a first plate of the first capacitor is electrically connected to the input terminal of the boost module to receive the boost input signal, and a second plate of the first capacitor is electrically connected to the gate electrode of the driving transistor; and

a second capacitor, wherein a first plate of the second capacitor is electrically connected to the gate electrode of the driving transistor, and a second plate of the second capacitor is configured to receive a first signal.

2. The pixel driving circuit according to claim 1 , wherein the boost module further comprises:

a boost sub-module, wherein an input terminal of the boost sub-module is configured as the input terminal of the boost module, and wherein the first plate of the first capacitor is electrically connected to an output terminal of the boost sub-module.

3. The pixel driving circuit according to claim 2 , wherein the boost sub-module comprises:

a first boost transistor, wherein a drain electrode of the first boost transistor is electrically connected to the first plate of the first capacitor, a source electrode of the first boost transistor is electrically connected to the input terminal of the boost module, a gate electrode of the first boost transistor is configured to receive a first boost control signal, and the first boost transistor is turned on in the first stage and the second stage; and

wherein the boost input signal has a first boost input voltage in the first stage, the boost input signal has a second boost input voltage in the second stage, and the second boost input voltage is greater than the first boost input voltage.

4. The pixel driving circuit according to claim 3 , wherein the boost sub-module further comprises:

a second boost transistor, wherein a drain electrode of the second boost transistor is electrically connected to the source electrode of the first boost transistor, a source electrode of the second boost transistor is electrically connected to the input terminal of the boost module, a gate electrode of the second boost transistor is configured to receive a second boost control signal, and the second boost transistor is turned on in the first stage and the second stage; and

wherein the gate electrode of the first boost transistor is electrically connected to the gate electrode of the driving transistor.

5. The pixel driving circuit of claim 1 , wherein the first signal is at a constant voltage during the first stage and the second stage.

6. The pixel driving circuit of claim 1 , wherein the second plate of the first capacitor is electrically connected to the source electrode of the driving transistor or a drain electrode of the driving transistor.

7. The pixel driving circuit according to claim 1 , wherein the second plate of the second capacitor is electrically connected to a drain electrode of the driving transistor; and

wherein the boost module further comprises:

a third capacitor; and

a boost switch connected in series with the third capacitor between the gate electrode of the driving transistor and the source electrode of the driving transistor,

wherein in the first stage and a third stage before the first stage, the boost switch is turned on to control the voltage of the gate electrode of the driving transistor to increase from a third voltage in the third stage to the first voltage.

8. The pixel driving circuit of claim 1 , further comprising:

a reset transistor, wherein a source electrode of the reset transistor is electrically connected to a reset line, a drain electrode of the reset transistor is electrically connected to the source electrode of the driving transistor, and a gate electrode of the reset transistor is configured to receive a reset control signal.

9. The pixel driving circuit according to claim 1 , wherein a capacitance value of the first capacitor is greater than a capacitance value of the second capacitor.

10. A display panel, comprising a plurality of pixel driving circuits each comprising:

a driving transistor connected in series with a light-emitting element between a first power supply line and a second power supply line, wherein a source electrode of the driving transistor is electrically connected to the light-emitting element;

a data transistor, wherein a source electrode of the data transistor is electrically connected to a data line, a drain electrode of the data transistor is electrically connected to a gate electrode of the driving transistor, and a gate electrode of the data transistor is configured to receive a data control signal; and

a boost module, wherein an input terminal of the boost module is configured to receive a boost input signal, and an output terminal of the boost module is electrically connected to the gate electrode of the driving transistor,

wherein in a first stage, the gate electrode of the driving transistor has a first voltage and the driving transistor is turned on to drive the light-emitting element to emit light at a first luminance;

in a second stage after the first stage, the boost module is configured to control a voltage of the gate electrode of the driving transistor to increase from the first voltage to a second voltage greater than the first voltage and the driving transistor is turned on to drive the light-emitting element to emit light at a second luminance greater than the first luminance; and

the boost module comprises:

a first capacitor, wherein a first plate of the first capacitor is electrically connected to the input terminal of the boost module to receive the boost input signal, and a second plate of the first capacitor is electrically connected to the gate electrode of the driving transistor; and

a second capacitor, wherein a first plate of the second capacitor is electrically connected to the gate electrode of the driving transistor, and a second plate of the second capacitor is configured to receive a first signal.

11. The display panel according to claim 10 , further comprising:

a data generating chip positioned on at least one side of the plurality of pixel driving circuits, wherein a plurality of data lines are electrically connected to the data generating chip to obtain data signals.

12. The display panel according to claim 11 , wherein an absolute value of a voltage value of one of the data signals corresponding to one of the pixel driving circuits far from the data generating chip is greater than an absolute value of a voltage value of one of the data signals corresponding to one of the pixel driving circuits close to the data generating chip.

13. The display panel of claim 11 , further comprising:

a signal generating chip positioned at least one side of the plurality of pixel driving circuits, wherein the input terminal of the boost module of each of the pixel driving circuits is electrically connected to the signal generating chip to obtain the boost input signal,

wherein the boost input signal has a first boost input voltage in the first stage, the boost input signal has a second boost input voltage in the second stage, and the second boost input voltage is greater than the first boost input voltage; and

wherein a difference between the second boost input voltage and the first boost input voltage corresponding to one of the pixel driving circuits away from the data generating chip is greater than a difference between the second boost input voltage and the first boost input voltage corresponding to one of the pixel driving circuits close to the data generating chip.

14. A display panel, comprising at least one pixel driving circuit, wherein the pixel driving circuit comprises:

a first transistor connected in series with a light-emitting element between a first power supply line and a second power supply line, wherein a source electrode of the first transistor is electrically connected to the light-emitting element;

a second transistor, wherein a source electrode of the second transistor is electrically connected to a first signal line, a drain electrode of the second transistor is electrically connected to a gate electrode of the first transistor, and a gate electrode of the second transistor is electrically connected to a second signal line; and

a first module, wherein an input terminal of the first module is electrically connected to a third signal line, an output terminal of the first module is electrically connected to the gate electrode of the first transistor, and a control terminal of the first module is electrically connected to a fourth signal line,

wherein in a first stage, the gate electrode of the first transistor has a first voltage and the first transistor is turned on to drive the light-emitting element to emit light at a first luminance;

in a second stage after the first stage, the first module is configured to control a voltage of the gate electrode of the first transistor to increase from the first voltage to a second voltage greater than the first voltage and the first transistor is turned on to drive the light-emitting element to emit light at a second luminance greater than the first luminance; and

wherein the first module comprises:

a first capacitor, wherein a first plate of the first capacitor is electrically connected to the input terminal of the first module, and a second plate of the first capacitor is electrically connected to the gate electrode of the first transistor; and

a second capacitor, wherein a first plate of the second capacitor is electrically connected to the gate electrode of the first transistor, and a second plate of the second capacitor is electrically connected to the source electrode of the first transistor or a drain electrode of the first transistor.

15. The display panel of claim 14 , wherein the first module further comprises:

a first sub-module, wherein an input terminal of the first sub-module is configured as the input terminal of the first module, and wherein the first plate of the first capacitor is electrically connected to an output terminal of the first sub-module.

16. The display panel according to claim 15 , wherein the first sub-module comprises:

a third transistor, wherein a drain electrode of the third transistor is electrically connected to the first plate of the first capacitor, a source electrode of the third transistor is electrically connected to the input terminal of the first module, and a gate electrode of the third transistor is electrically connected to a fifth signal line.

17. The display panel according to claim 16 , wherein the first sub-module further comprises:

a fourth transistor, wherein a drain electrode of the fourth transistor is electrically connected to the source electrode of the third transistor, a source electrode of the fourth transistor is electrically connected to the input terminal of the first module, and a gate electrode of the fourth transistor is electrically connected to a sixth signal line different from the gate electrode of the first transistor;

wherein the gate electrode of the third transistor is electrically connected to the gate electrode of the first transistor.

18. The display panel according to claim 14 , wherein the second plate of the second capacitor is electrically connected to the drain electrode of the first transistor, and

wherein the first module further comprises:

a third capacitor; and

a first switch connected in series with the third capacitor between the gate electrode of the first transistor and the source electrode of the first transistor,

wherein the first switch is configured to control the third capacitor to be electrically connected between the gate electrode of the first transistor and the source electrode of the first transistor.

19. The display panel according to claim 14 , wherein the pixel driving circuit further comprises:

a fifth transistor, wherein a source electrode of the fifth transistor is electrically connected to a seventh signal line, a drain electrode of the fifth transistor is electrically connected to the source electrode of the first transistor, and a gate electrode of the fifth transistor is electrically connected to an eighth signal line.

20. The display panel according to claim 14 , wherein the at least one pixel driving circuit comprises a plurality of pixel driving circuits,

the display panel further comprising:

a data generating chip positioned on at least one side of the plurality of pixel driving circuits, wherein a plurality of data lines are electrically connected to the data generating chip to obtain data signals.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2022
From: HU, LIANG
To: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
Reel/Frame 061300/0004 →
Priority Claims (1)
CN 202210615801.3 · May 31, 2022 · national
Continuity (1)
Related Publication 20240221640A1 · Jul 4, 2024
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