IP Library › Granted Patent US 12,394,637
Granted Patent B2
US 12,394,637 · App. 17/643,231 · Granted Aug 19, 2025

Semiconductor device and method of processing strip of electrical components using mesh jig

Inventors: JoonSung Park (Incheon, KR); JiSu Han (Incheon, KR); WonSang Rhee (Incheon, KR)
Assignee: STATS ChipPAC Pte. Ltd.
H01L21/568H01L21/565H01L21/6835H01L24/16H01L24/81H01L24/97H01L2224/16227H01L2924/3511
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Quick Facts
Patent No.
US 12,394,637
App. No.
17/643,231
Granted
Aug 19, 2025
Kind
B2
Abstract

A semiconductor device has an interconnect substrate and an electrical component disposed over the substrate. A first carrier including a window is disposed over the interconnect substrate with the electrical component disposed within the window. A second carrier is disposed over the first carrier with a plurality of posts extending through the first carrier. The substrate is disposed over a third carrier. The posts may extend through the first carrier outside a footprint of the substrate. Alternatively, at least one of the posts extend through an opening in the substrate and the remaining posts are outside the footprint of the substrate. A plurality of pins extends from the second carrier to a dummy area of the substrate. Openings can be formed in a surface of the second carrier. The combination of first carrier, second carrier, and third carrier constitutes a mesh jig to support the strip of electrical components.

Claims (63)

1. A method of making a semiconductor device, comprising:

providing a first substrate;

disposing an electrical component over the first substrate;

disposing a first carrier including a window over the first substrate, wherein the first carrier surrounds the electrical component as disposed within the window;

disposing a second carrier over the first carrier to enclose the electrical component with the first carrier and second carrier; and

providing a plurality of posts extending from the second carrier, wherein a sharpened distal end of the posts relative to the second carrier penetrates through penetrable material of the first carrier and further penetrates partially but not completely through penetrable material of the first substrate to hold the first carrier and second carrier in place by nature of the sharpened distal end of the posts contacting the penetrable material of the first substrate.

2. The method of claim 1 , further including:

providing a third carrier; and

disposing the first substrate over the third carrier, wherein the plurality of posts extending from the second carrier further extend into the third carrier.

3. The method of claim 1 , further including disposing a second substrate over the first substrate, wherein the posts extend through the first carrier outside a footprint of the second substrate.

4. The method of claim 1 , wherein at least one of the posts extends through an opening in the first substrate.

5. The method of claim 1 , wherein the plurality of posts extends from the second carrier to a dummy area of the first substrate.

6. The method of claim 1 , further including forming a plurality of openings in a surface of the second carrier.

7. The method of claim 1 , wherein disposing the electrical component over the first substrate further includes: disposing a plurality of electrical components over the first substrate, wherein the window of the carrier is sufficiently large to enclose the electrical components.

8. The method of claim 1 , further including:

depositing an encapsulant around the electrical component;

removing the first substrate to expose the sharpened distal end of the posts;

removing the first carrier; and

removing the second carrier leaving the encapsulant deposited around the electrical component.

9. A method of making a semiconductor device, comprising:

providing a substrate;

disposing a first carrier including a window over the substrate;

disposing a second carrier over the first carrier; and

providing a plurality of posts extending from the second carrier, wherein a pointed distal end of the posts relative to the second carrier penetrates through penetrable material of the first carrier and further penetrates partially but not completely through penetrable material of the substrate to hold the first carrier and second carrier in place as the pointed distal end of the posts contacts the penetrable material of the substrate.

10. The method of claim 9 , further including:

providing a third carrier; and

disposing the substrate over the third carrier.

11. The method of claim 9 , wherein the posts extend through the first carrier outside a footprint of the substrate.

12. The method of claim 9 , wherein at least one of the posts extends through an opening in the substrate.

13. The method of claim 9 , wherein the plurality of posts extends from the second carrier to a dummy area of the substrate.

14. The method of claim 9 , further including forming a plurality of openings in a surface of the second carrier.

15. The method of claim 9 , further including disposing an electrical component over the substrate.

16. The method of claim 15 , further including:

depositing an encapsulant around the electrical component;

removing the substrate to expose the sharpened distal end of the posts;

removing the first carrier; and

removing the second carrier leaving the encapsulant deposited around the electrical component.

17. The method of claim 9 , further including disposing a plurality of electrical components over the first substrate, wherein the window of the carrier is sufficiently large to enclose the electrical components.

18. A semiconductor device, comprising:

a first substrate;

an electrical component disposed over the first substrate;

a first carrier including a window disposed over the first substrate, wherein the first carrier surrounds the electrical component as disposed within the window;

a second carrier disposed over the first carrier; and

a plurality of posts extending from the second carrier, wherein a sharpened distal end of the posts relative to the second carrier penetrates through penetrable material of the first carrier and further penetrates partially but not completely through penetrable material of the first substrate to hold the first carrier and second carrier in place by nature of the sharpened distal end of the posts contacting the penetrable material of the first substrate.

19. The semiconductor device of claim 18 , further including a third carrier, wherein the first substrate is disposed over the third carrier.

20. The semiconductor device of claim 18 further including a second substrate disposed over the first substrate, wherein the posts extend through the first carrier outside a footprint of the second substrate.

21. The semiconductor device of claim 18 , wherein at least one of the posts extends through an opening in the first substrate.

22. The semiconductor device of claim 18 , wherein the plurality of posts extends from the second carrier to a dummy area of the first substrate.

23. The semiconductor device of claim 18 , further including a plurality of openings formed in a surface of the second carrier.

24. The semiconductor device of claim 18 , wherein the electrical component disposed over the first substrate further includes: a plurality of electrical components disposed over the first substrate, wherein the window of the carrier is sufficiently large to enclose the electrical components.

25. The semiconductor device of claim 18 , wherein the posts have a circular base in contact with the second carrier and narrow to the sharpened distal end.

26. A semiconductor device, comprising:

a substrate;

a first carrier including a window disposed over the substrate;

a second carrier disposed over the first carrier; and

a plurality of posts extending from the second carrier, wherein a pointed distal end of the posts relative to the second carrier penetrates through penetrable material of the first carrier and further penetrates partially but not completely through penetrable material of the substrate to hold the first carrier and second carrier in place as the pointed distal end of the posts contacts the penetrable material of the substrate.

27. The semiconductor device of claim 26 , further including a third carrier, wherein the substrate is disposed over the third carrier.

28. The semiconductor device of claim 26 , wherein the posts extend through the first carrier outside a footprint of the substrate.

29. The semiconductor device of claim 26 , wherein at least one of the posts extends through an opening in the substrate.

30. The semiconductor device of claim 26 , wherein the plurality of posts extends from the second carrier to a dummy area of the substrate.

31. The semiconductor device of claim 26 , further including a plurality of openings formed in a surface of the second carrier.

32. The semiconductor device of claim 26 , further including a plurality of electrical components disposed over the first substrate, wherein the window of the carrier is sufficiently large to enclose the electrical components.

33. The semiconductor device of claim 26 , wherein the posts have a circular base in contact with the second carrier and narrow to the pointed end.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 14, 2021
From: PARK, JOONSUNG; HAN, JISU; RHEE, WONSANG
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 058380/0828 →
Continuity (1)
Related Publication 20230178384A1 · Jun 8, 2023
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