Granted Patent B2

US 12,395,082 · App. 18/351,872 · Granted Aug 19, 2025

Inventors: Jang Hyuck Lee (Sungnam-si, KR); Seongnam Kim (Namyangju-si, KR)

Assignee: NXP B.V.

H02M3/1584H02M1/0025H02M1/088

Abstract

Claims (62)

1. A switching regulator circuit, comprising:

a power supply input;

a voltage reference;

a power output;

a high-side switch coupled between the power supply input and the power output;

a low-side switch coupled between a ground reference and the power output;

a driver circuit coupled to the high-side switch and the low-side switch;

a low-power comparator coupled to receive the voltage reference and the power output;

a high-power comparator having a first input and a second input;

wherein the first input is coupled to a compensation capacitor and a first switch;

wherein the second input is coupled to a current sense ramp;

wherein the current sense ramp is coupled to the power output;

wherein the first switch is coupled to an error amplifier; and

wherein the error amplifier is coupled to receive the voltage reference and the power output;

a second switch coupled to the low-power comparator, the high-power comparator, and the driver circuit;

a controller coupled to the first switch and the second switch;

wherein the controller is configured to control the first switch and the second switch to place the switching regulator circuit in either a high-power mode or a low-power mode.

2. The switching regulator circuit of claim 1 :

wherein when the first switch is open the compensation capacitor is prevented from being discharged through the error amplifier.

3. The switching regulator circuit of claim 1 :

wherein the controller is configured to place the switching regulator circuit in the high-power mode by increasing a time the high-side switch couples the power supply input to the power output.

4. The switching regulator circuit of claim 3 :

wherein the controller is configured to place the switching regulator circuit in the low-power mode by decreasing the time the high-side switch couples the power supply input to the power output.

5. The switching regulator circuit of claim 1 :

wherein in the low-power mode the controller is configured to disable the error amplifier.

6. The switching regulator circuit of claim 1 :

wherein in the low-power mode the controller is configured to disable the error amplifier, the high-power comparator, and the current sense ramp and enable the low-power comparator.

7. The switching regulator circuit of claim 1 :

wherein in the high-power mode the controller is configured to enable the error amplifier, the high-power comparator, and the current sense ramp, and disable the low-power comparator.

8. The switching regulator circuit of claim 1 :

further comprising a quick-start circuit coupled to the controller;

wherein the quick-start circuit is configured to charge a set of capacitors when the switching regulator is in the low-power mode.

9. The switching regulator circuit of claim 8 :

wherein the set of capacitors are parasitic capacitors in the switching regulator circuit.

10. The switching regulator circuit of claim 8 :

wherein the quick-start circuit is configured to stop charging the set of parasitic capacitors when the switching regulator is in the high-power mode.

11. The switching regulator circuit of claim 8 :

wherein the set of capacitors are in the error amplifier.

12. The switching regulator circuit of claim 8 :

wherein the set of capacitors are in the high-power comparator and the current sense ramp.

13. The switching regulator circuit of claim 8 :

wherein the quick-start circuit includes an inverter and a capacitor.

14. The switching regulator circuit of claim 8 :

wherein the quick-start circuit includes a one-shot and a mosfet.

15. The switching regulator circuit of claim 1 :

further comprising a timer circuit;

wherein the timer circuit is configured to periodically charge the compensation capacitor to a preset voltage during the low-power mode.

16. The switching regulator circuit of claim 1 :

further comprising a timer circuit coupled to the first switch;

wherein the timer circuit is configured to periodically close the first switch during the low-power mode.

17. The switching regulator circuit of claim 1 :

further comprising a timer circuit coupled to the first switch and the error amplifier;

wherein in the low-power mode in a first time period the first switch is open and the error amplifier is disabled;

wherein in the low-power mode in a second time period the timer circuit closes the first switch and enables the error amplifier for a predetermined time period; and

wherein after the predetermined time period the timer circuit opens the first switch and disables the error amplifier.

18. The switching regulator circuit of claim 1 :

further comprising an on-time control circuit coupled between the second switch and the driver circuit;

wherein the on-time control circuit is configured to control a time period when the high-side switch is turned on.

19. A voltage converter including the switching regulator circuit of claim 1 :

wherein the voltage converter is in a buck configuration.

20. A voltage converter including the switching regulator circuit of claim 1 :

wherein the voltage converter is in a boost configuration.

Assignments (1)

Continuity (1)

References Cited (18)