Enlarging active areas of displays in electronic devices
This document describes systems and techniques directed at enlarging active areas of displays in electronic devices. In aspects, a display includes a grid of transistors positioned within a display panel module to control an illumination of one or more electroluminescent layers. Routing lines extend from one or more transistors of the grid of transistors to at least one electroluminescent layer. In this way, the at least one electroluminescent layer can be positioned away from the grid of transistors and disposed above portions of display panel module driving circuitry. As a result, active areas of displays can be enlarged and information content can be maximized without a panel border area allotted to the display panel module driving circuitry surrounding transistors having to be reduced.
1. A display comprising:
a cover layer positioned as a topmost layer;
an electroluminescent layer positioned underneath the cover layer and configured to emit light when a voltage is applied across a cathode and an anode;
a transistor configured to control an electrical activation of the electroluminescent layer by controlling the voltage across the cathode and the anode;
driving circuitry positioned underneath the cover layer and operatively coupled to the transistor, the driving circuitry configured to control the transistor;
a shielding conductor layer configured to shield the anode from parasitic coupling capacitances originating from the driving circuitry, the shielding conductor layer operatively coupled to a direct current reference voltage;
a routing line connected to an electrode of the transistor; and
a routing metal operatively coupling the anode of the electroluminescent layer to the routing line, the routing metal extending from the routing line above at least portions of the driving circuitry, and
the electroluminescent layer disposed above the at least portions of the driving circuitry such that the electroluminescent layer is positioned between the cover layer and the driving circuitry.
2. The display of claim 1 , wherein the driving circuitry comprises at least one of a compensation capacitor, a high-level power supply voltage source, a demultiplexer circuit, a gate driver on array, source lines, or a low-level power supply voltage source.
3. The display of claim 2 , wherein:
the driving circuitry comprises the demultiplexer circuit and the gate driver on array; and
the routing metal and the electroluminescent layer are disposed above at least one of the demultiplexer circuit or the gate driver on array.
4. The display of claim 1 , wherein the shielding conductor layer is disposed at least partially underneath the routing metal.
5. The display of claim 1 , wherein:
the electroluminescent layer is one of a plurality of electroluminescent layers, each electroluminescent layer of the plurality of electroluminescent layers having a respective cathode and a respective anode, and wherein the plurality of electroluminescent layers form an array;
the transistor is one of a plurality of transistors, each transistor of the plurality of transistors being associated with a respective electroluminescent layer of the plurality of electroluminescent layers, and wherein the plurality of transistors form a grid;
the routing line is one of a plurality of routing lines, each routing line of the plurality of routing lines being operatively coupled to a respective transistor of the plurality of transistors; and
the routing metal is one of a plurality of routing metals, each routing metal of the plurality of routing metals operatively coupling the anode of a respective electroluminescent layer of the plurality of electroluminescent layers to a respective routing line of the plurality of routing lines.
6. The display of claim 5 , wherein:
the array of electroluminescent layers comprises a uniform density of electroluminescent layers;
the grid of transistors comprises a uniform density of transistors; and
the array of electroluminescent layers comprises a larger area than the grid of transistors.
7. The display of claim 5 , wherein:
the array of electroluminescent layers comprises an inner region and an outer region;
the inner region comprises a first density of electroluminescent layers; and
the outer region comprises a second density of electroluminescent layers.
8. The display of claim 7 , wherein the first density of electroluminescent layers is greater than the second density of electroluminescent layers.
9. The display of claim 7 , wherein one or more electroluminescent layers in the outer region are disposed above at least portions of the driving circuitry.
10. The display of claim 7 , wherein the outer region extends along an entire outer perimeter of the array of electroluminescent layers.
11. The display of claim 1 , wherein the display comprises an elliptical form factor.
12. The display of claim 1 , wherein the electroluminescent layer comprises a red diode, a green diode, a blue diode, or an infrared diode.
13. The display of claim 1 , wherein the display further comprises:
an opaque border bonded to a bottom face of the cover layer, the opaque border having an outer diameter and an inner diameter, and wherein a thickness between the inner diameter and the outer diameter is based on a placement of the electroluminescent layer above the at least portions of the driving circuitry.
14. A wearable device comprising:
a housing;
one or more processors disposed within the housing; and
a display operably coupled to the one or more processors and at least partially disposed within the housing, the display comprising:
a cover layer positioned as a topmost layer, the cover layer including an opaque border having an outer diameter and an inner diameter;
an electroluminescent layer positioned underneath the cover layer and configured to emit light when a voltage is applied across a cathode and an anode;
a transistor configured to control an electrical activation of the electroluminescent layer by controlling the voltage across the cathode and the anode;
driving circuitry positioned underneath the cover layer and operatively coupled to the transistor, the driving circuitry configured to control the transistor;
a routing line connected to an electrode of the transistor; and
a routing metal operatively coupling the anode of the electroluminescent layer to the routing line, the routing metal extending from the routing line above at least portions of the driving circuitry, and
the electroluminescent layer disposed above the at least portions of the driving circuitry such that the electroluminescent layer is positioned between the cover layer and the driving circuitry, and a thickness between the inner diameter and the outer diameter based on a placement of the electroluminescent layer above the at least portions of the driving circuitry.
15. The wearable device of claim 14 , wherein:
the electroluminescent layer is one of a plurality of electroluminescent layers, each electroluminescent layer of the plurality of electroluminescent layers having a respective cathode and a respective anode, and wherein the plurality of electroluminescent layers form an array;
the transistor is one of a plurality of transistors, each transistor of the plurality of transistors being associated with a respective electroluminescent layer of the plurality of electroluminescent layers, and wherein the plurality of transistors form a grid;
the routing line is one of a plurality of routing lines, each routing line of the plurality of routing lines being operatively coupled to a respective transistor of the plurality of transistors; and
the routing metal is one of a plurality of routing metals, each routing metal of the plurality of routing metals operatively coupling the anode of a respective electroluminescent layer of the plurality of electroluminescent layers to a respective routing line of the plurality of routing lines.
16. The wearable device of claim 15 , wherein:
the array of electroluminescent layers comprises a uniform density of electroluminescent layers;
the grid of transistors comprises a uniform density of transistors; and
the array of electroluminescent layers comprises a larger area than the grid of transistors.
17. The wearable device of claim 15 , wherein:
the array of electroluminescent layers comprises an inner region and an outer region;
the inner region comprises a first density of electroluminescent layers; and
the outer region comprises a second density of electroluminescent layers.
18. The wearable device of claim 17 , wherein at least one of:
the first density of electroluminescent layers is greater than the second density of electroluminescent layers; or
one or more electroluminescent layers in the outer region are disposed above at least portions of the driving circuitry.
19. The wearable device of claim 17 , wherein the display comprises an elliptical form factor.
20. The wearable device of claim 14 , wherein the display further comprises:
a shielding conductor layer configured to shield the anode from parasitic coupling capacitances originating from the driving circuitry, the shielding conductor layer operatively coupled to a direct current reference voltage.
21. A display comprising:
a cover layer positioned as a topmost layer, the cover layer including an opaque border having an outer diameter and an inner diameter;
an electroluminescent layer positioned underneath the cover layer and configured to emit light when a voltage is applied across a cathode and an anode;
a transistor configured to control an electrical activation of the electroluminescent layer by controlling the voltage across the cathode and the anode;
driving circuitry positioned underneath the cover layer and operatively coupled to the transistor, the driving circuitry configured to control the transistor;
a routing line connected to an electrode of the transistor; and
a routing metal operatively coupling the anode of the electroluminescent layer to the routing line, the routing metal extending from the routing line above at least portions of the driving circuitry, and
the electroluminescent layer disposed above the at least portions of the driving circuitry such that the electroluminescent layer is positioned between the cover layer and the driving circuitry, and a thickness between the inner diameter and the outer diameter based on a placement of the electroluminescent layer above the at least portions of the driving circuitry.