Debugging of accelerator circuit for mathematical operations using packet limit breakpoint
Embodiments of the present disclosure relate to debugging of an accelerator circuit using a packet limit breakpoint. A vector circuit reads a subset of instruction packets from an instruction memory and receives a portion of input data from a data memory corresponding to the subset of instruction packets. The vector circuit executes a set of vector operations in accordance with multiple instruction packets from the subset using data from the received portion of input data identified in the multiple instruction packets to generate output data. A program counter control circuit coupled to the instruction memory triggers a breakpoint in a program stored in the instruction memory causing the accelerator circuit to stop executing remaining instruction packets in the program following the multiple instruction packets responsive to a number of instruction packets executed in the program from a time instant of an event reaching a predetermined number.
1. An accelerator circuit, comprising:
at least one memory storing a program that includes a plurality of instruction packets;
a vector circuit coupled to the at least one memory and configured to:
read a first subset of the instruction packets from the at least one memory;
obtain a portion of input data corresponding to the first subset of instruction packets; and
execute a set of vector operations based on a second subset of the instruction packets from the first subset using data from the obtained portion of input data identified in the second subset of instruction packets to generate output data, wherein the second subset comprises at least two instruction packets from the first subset; and
a program counter control circuit coupled to the at least one memory and configured to trigger a breakpoint in the program to cause the accelerator circuit to stop executing remaining instruction packets in the program that follow the at least two instruction packets based on a number of instructions packets executed in the second subset reaching a predetermined threshold.
2. The accelerator circuit of claim 1 , wherein each of the plurality of instruction packets comprises a plurality of instructions executed in parallel by the accelerator circuit.
3. The accelerator circuit of claim 1 , further comprising:
an advanced extensible interface (AXI) slave port configured to evaluate a state of the accelerator circuit responsive to the triggering of the breakpoint.
4. The accelerator circuit of claim 1 , wherein the program counter control circuit is configured to trigger the breakpoint based on an event.
5. The accelerator circuit of claim 4 , wherein the event comprises a software reset of the accelerator circuit.
6. The accelerator circuit of claim 5 , wherein the predetermined threshold is equal to a number of instruction packets in a packet limit register of the program counter control circuit, and wherein the program counter control circuit is further configured to trigger the breakpoint responsive to the number of instruction packets executed in the program after the software reset of the accelerator circuit being equal to the predetermined threshold.
7. The accelerator circuit of claim 4 , wherein the event comprises resetting a packet count register of the program counter control circuit.
8. The accelerator circuit of claim 7 , wherein the predetermined threshold is equal to a number of instruction packets in a packet limit register of the program counter control circuit, and wherein the program counter control circuit is further configured to trigger the breakpoint responsive to the number of instruction packets executed in the program after the resetting of the packet count register being equal to the predetermined threshold.
9. The accelerator circuit of claim 1 , wherein the accelerator circuit is integrated into an image signal processor circuit or a neural processor circuit.
10. A method, comprising:
reading a first subset of a plurality of instruction packets of a program from at least one memory of an accelerator circuit;
obtaining a portion of input data corresponding to the first subset of instruction packets;
executing a set of vector operations based on a second subset of the instruction packets from the first subset using data from the obtained portion of input data identified in the second subset of instruction packets to generate output data; and
triggering, by a program counter control circuit of the accelerator circuit, a breakpoint in the program based on a reset event to cause the accelerator circuit to stop executing remaining instruction packets in the program.
11. The method of claim 10 , wherein each of the plurality of instruction packets comprises a plurality of instructions executed in parallel at the accelerator circuit.
12. The method of claim 10 , further comprising:
evaluating a state of the accelerator circuit via an advanced extensible interface (AXI) slave port of the accelerator circuit.
13. The method of claim 10 , wherein the reset event comprises a software reset of the accelerator circuit.
14. The method of claim 13 , wherein triggering the breakpoint in the program based on the reset event comprises triggering the breakpoint responsive to a number of instruction packets of the plurality of instruction packets executed in the program after the software reset of the accelerator circuit being equal to a number of instruction packets in a packet limit register of the program counter control circuit.
15. The method of claim 10 , wherein the reset event comprises a reset of a packet count register of the program counter control circuit.
16. The method of claim 15 , wherein triggering the breakpoint in the program based on the reset event comprises triggering the breakpoint responsive to a number of instruction packets of the plurality of instruction packets executed in the program after reset of the packet count register being equal to a number of instruction packets in a packet limit register of the program counter control circuit.
17. The method of claim 10 , wherein the accelerator circuit is integrated into an image signal processor circuit or a neural processor circuit.
18. A system, comprising:
a system memory configured to store input data; and
an accelerator circuit coupled to the system memory and comprising:
a data memory configured to receive and store the input data from the system memory;
an instruction memory configured to store a program that includes a plurality of instruction packets;
a vector circuit coupled to the instruction memory and configured to:
read a first subset of the instruction packets from the instruction memory;
obtain a portion of the input data corresponding to the first subset of instruction packets; and
execute a set of vector operations based on a second subset of the instruction packets from the first subset using data from the obtained portion of input data identified in the second subset of instruction packets to generate output data; and
a program counter control circuit coupled to the instruction memory and configured to trigger a breakpoint in the program based on a reset event to cause the accelerator circuit to stop executing remaining instruction packets in the program.
19. The system of claim 18 , wherein the reset event is one of software reset of the accelerator circuit or a reset of a packet count register of the program counter control circuit, and wherein the program counter control circuit is further configured to trigger the breakpoint responsive to a number of instruction packets of the plurality of instruction packets executed in the program after the reset event being equal to a number of instruction packets in a packet limit register of the program counter control circuit, each of the plurality of instruction packets comprising a plurality of instructions executed in parallel by the accelerator circuit.
20. A device, comprising:
at least one memory storing a program that includes a plurality of instruction packets;
a circuit coupled to the at least one memory and configured to:
read a first subset of the instruction packets from the at least one memory;
obtain a portion of input data corresponding to the first subset of instruction packets; and
execute a set of operations based on a second subset of the instruction packets from the first subset using data from the obtained portion of input data identified in the second subset of instruction packets to generate output data, wherein the second subset comprises at least two instruction packets from the first subset; and
a program counter control circuit coupled to the at least one memory and configured to trigger a breakpoint in the program to cause the circuit to stop executing remaining instruction packets in the program that follow the at least two instruction packets based on a number of instructions packets executed in the second subset reaching a predetermined threshold.
21. The device of claim 20 , wherein the program counter control circuit is configured to trigger the breakpoint based on an event.