IP Library › Granted Patent US 12,400,605
Granted Patent B2
US 12,400,605 · App. 18/560,716 · Granted Aug 26, 2025

Semiconductor device, display apparatus, and electronic device

Inventors: Munehiro Kozuma (Atsugi, JP); Tatsuya Onuki (Atsugi, JP); Takanori Matsuzaki (Atsugi, JP); Minato Ito (Atsugi, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
G09G3/3275G09G3/3233G09G2300/0842G09G2310/0243G09G2310/0291G09G2330/021H10D30/6734H10D30/6755H10K59/131
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Quick Facts
Patent No.
US 12,400,605
App. No.
18/560,716
Filed
Nov 14, 2023
Granted
Aug 26, 2025
Kind
B2
Art Unit
2625
USPC
345/204
Abstract

A semiconductor device having redundancy is provided. The semiconductor device includes a first driver circuit, a second driver circuit, a first selection circuit, a second selection circuit, and a switch circuit. An output terminal of the first driver circuit is electrically connected to an input terminal of the first selection circuit and a first terminal of the switch circuit, and an output terminal of the second driver circuit is electrically connected to an input terminal of the second selection circuit and a second terminal of the switch circuit.

Claims (34)

1. A semiconductor device comprising a circuit, the circuit comprising:

a first driver circuit comprising a first signal generation circuit and a first switch;

a second driver circuit comprising a second signal generation circuit and a second switch;

a switch circuit comprising a third switch;

a first selection circuit comprising a fourth switch and a fifth switch;

a second selection circuit comprising a sixth switch and a seventh switch;

a first terminal of the circuit;

a second terminal of the circuit;

a third terminal of the circuit; and

a fourth terminal of the circuit,

wherein a potential of a fifth terminal is input to the first driver circuit through a first inverter,

wherein a potential of a sixth terminal is input to the second driver circuit through a second inverter,

wherein the potential of the fifth terminal and the potential of the sixth terminal is input to an XOR circuit,

wherein a potential output from the XOR circuit is input to a control terminal of the third switch,

wherein the first signal generation circuit is configured to generate a first data signal,

wherein the second signal generation circuit is configured to generate a second data signal,

wherein the first signal generation circuit is electrically connected to a first terminal of the first switch,

wherein a second terminal of the first switch is electrically connected to a first terminal of the third switch, a first terminal of the fourth switch, and a first terminal of the fifth switch,

wherein the second signal generation circuit is electrically connected to a first terminal of the second switch,

wherein a second terminal of the second switch is electrically connected to a second terminal of the third switch, a first terminal of the sixth switch, and a first terminal of the seventh switch,

wherein a second terminal of the fourth switch is electrically connected to the first terminal of the circuit,

wherein a second terminal of the fifth switch is electrically connected to the second terminal of the circuit,

wherein a second terminal of the sixth switch is electrically connected to the third terminal of the circuit, and

wherein a second terminal of the seventh switch is electrically connected to the fourth terminal of the circuit.

2. The semiconductor device according to claim 1 ,

wherein the first switch, the second switch, and the third switch are each an analog switch.

3. A display apparatus comprising:

the semiconductor device according to claim 1 ; and

a first pixel circuit capable of being electrically connected to the first terminal and the second terminal of the circuit,

wherein, when the first pixel circuit is electrically connected to one of the first terminal and the second terminal of the circuit, the first pixel circuit is not electrically connected to the other of the first terminal and the second terminal of the circuit.

4. A display apparatus comprising:

the semiconductor device according to claim 1 ;

a first pixel circuit electrically connected to the first terminal of the circuit; and

a second pixel circuit electrically connected to the second terminal of the circuit.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 14, 2023
From: KOZUMA, MUNEHIRO; ONUKI, TATSUYA; MATSUZAKI, TAKANORI; ITO, MINATO
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 065555/0254 →
Priority Claims (1)
JP 2021-089485 · May 27, 2021 · national
Continuity (1)
Related Publication 20240265882A1 · Aug 8, 2024
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