Input sampling system and method, storage medium, and computer device
An input sampling system and method, a storage medium, and a computer device involve: a signal processing circuit configured to receive an initial chip select signal and a command/address signal, and broaden a pulse width of a valid signal in the initial chip select signal backward to obtain a first chip select signal, to control an end moment of a valid signal in the first chip select signal to be later than an end moment of a valid signal in the command/address signal; and an input sampling circuit connected to the signal processing circuit, and configured to receive the command/address signal, the first chip select signal, and a clock pulse signal and sample the command/address signal according to the first chip select signal and the clock pulse signal.
1. An input sampling system, comprising:
a signal processing circuit, configured to receive an initial chip select signal and a command/address signal, and broaden a pulse width of a valid signal in the initial chip select signal backward to obtain and output a first chip select signal, to control an end moment of a valid signal in the first chip select signal to be later than an end moment of a valid signal in the command/address signal; and
an input sampling circuit, connected to the signal processing circuit, and configured to receive the command/address signal, the first chip select signal, and a clock pulse signal, and sample the command/address signal according to the first chip select signal and the clock pulse signal.
2. The input sampling system according to claim 1 , further comprising:
a signal generation circuit, connected to the signal processing circuit, and configured to send the initial chip select signal and the command/address signal, and control an arrival moment of the valid signal in the initial chip select signal to be earlier than an arrival moment of the valid signal in the command/address signal when a moment at which the signal generation circuit sends the initial chip select signal is earlier than a moment at which the signal generation circuit sends the command/address signal.
3. The input sampling system according to claim 1 , wherein the signal processing circuit is further configured to broaden the pulse width of the valid signal in the initial chip select signal forward, to control an arrival moment of the valid signal in the first chip select signal to be earlier than an arrival moment of the valid signal in the command/address signal.
4. The input sampling system according to claim 3 , wherein the signal processing circuit comprises:
an initial chip select signal receiving sub-circuit, configured to receive the initial chip select signal and delay the initial chip select signal to output a second chip select signal;
a command/address signal receiving sub-circuit, configured to receive the command/address signal and delay the command/address signal to output a first command/address signal, wherein an absolute delay of the initial chip select signal receiving sub-circuit is less than an absolute delay of the command/address signal receiving sub-circuit; and
a logic processing sub-circuit, connected to the initial chip select signal receiving sub-circuit and the command/address signal receiving sub-circuit, and configured to delay the second chip select signal to obtain a third chip select signal and obtain the first chip select signal according to the second chip select signal and the third chip select signal, wherein the arrival moment of the valid signal in the first chip select signal is the same as an arrival moment of a valid signal in the second chip select signal, and the end moment of the valid signal in the first chip select signal is the same as an end moment of a valid signal in the third chip select signal.
5. The input sampling system according to claim 4 , wherein the initial chip select signal receiving sub-circuit comprises a first comparator provided with a non-inverting input terminal for inputting the initial chip select signal, an inverting input terminal for inputting a first reference voltage, and an output terminal for outputting the second chip select signal, wherein if a voltage of the initial chip select signal is higher than the first reference voltage, the second chip select signal is a high-level signal, and if the voltage of the initial chip select signal is lower than the first reference voltage, the second chip select signal is a low-level signal, and the low-level signal in the second chip select signal is the valid signal in the second chip select signal.
6. The input sampling system according to claim 4 , wherein the command/address signal receiving sub-circuit comprises a second comparator provided with a non-inverting input terminal for inputting the command/address signal, an inverting input terminal for inputting a second reference voltage, and an output terminal for outputting the first command/address signal, wherein if a voltage of the command/address signal is higher than the second reference voltage, the first command/address signal is a high-level signal, and if the voltage of the command/address signal is lower than the second reference voltage, the first command/address signal is a low-level signal.
7. The input sampling system according to claim 4 , wherein the logic processing sub-circuit comprises:
a third comparator, provided with a non-inverting input terminal for receiving a first clock signal and an inverting input terminal for receiving a second clock signal, and configured to compare the first clock signal with the second clock signal to output the clock pulse signal;
a flip-flop, provided with a first input terminal connected to an output terminal of the initial chip select signal receiving sub-circuit for receiving the second chip select signal and a second input terminal connected to the third comparator for receiving the clock pulse signal, and configured to delay the second chip select signal according to the clock pulse signal to obtain the third chip select signal; and
an AND gate, provided with a first input terminal connected to the output terminal of the initial chip select signal receiving sub-circuit for receiving the second chip select signal and a second input terminal connected to an output terminal of the flip-flop for receiving the third chip select signal, and configured to perform logic AND on the second chip select signal and the third chip select signal to obtain the first chip select signal.
8. The input sampling system according to claim 7 , wherein the flip-flop is a rising edge flip-flop, and an arrival moment of the valid signal in the third chip select signal outputted by the rising edge flip-flop is the same as an arrival moment of a first rising edge of the clock pulse signal after the valid signal in the second chip select signal arrives.
9. The input sampling system according to claim 7 , wherein the clock pulse signal is a periodic signal, and the valid signals in the initial chip select signal, the second chip select signal, the third chip select signal, and the first chip select signal are all low-level signals.
10. The input sampling system according to claim 7 , wherein the input sampling circuit comprises:
an input signal acquisition sub-circuit, provided with a first input terminal connected to an output terminal of the AND gate for receiving the first chip select signal and a second input terminal connected to the command/address signal receiving sub-circuit for receiving the first command/address signal, and configured to sample the first command/address signal during a valid signal period of the first chip select signal to obtain a command/address input signal; and
an input sampling sub-circuit, provided with a first input terminal connected to an output terminal of the input signal acquisition sub-circuit for receiving the command/address input signal and a second input terminal connected to an output terminal of the third comparator for receiving the clock pulse signal, and configured to sample the command/address input signal on the basis of the clock pulse signal to obtain a command/address output signal.
11. The input sampling system according to claim 10 , wherein the input signal acquisition sub-circuit comprises:
a NOT gate, provided with an input terminal connected to the command/address signal receiving sub-circuit for receiving the first command/address signal, and configured to invert the first command/address signal to obtain a second command/address signal; and
a NOR gate, provided with a first input terminal connected to the output terminal of the AND gate for receiving the first chip select signal and a second input terminal connected to an output terminal of the NOT gate for receiving the second command/address signal, and configured to perform logic NOR on the second command/address signal and the first chip select signal to obtain the command/address input signal.
12. An input sampling method, comprising:
acquiring an initial chip select signal and a command/address signal;
broadening a pulse width of a valid signal in the initial chip select signal backward to obtain a first chip select signal, to control an end moment of a valid signal in the first chip select signal to be later than an end moment of a valid signal in the command/address signal;
acquiring a clock pulse signal; and
sampling the command/address signal on the basis of the first chip select signal and the clock pulse signal.
13. The input sampling method according to claim 12 , further comprising:
broadening the pulse width of the valid signal in the initial chip select signal forward, to control an arrival moment of the valid signal in the first chip select signal to be earlier than an arrival moment of the valid signal in the command/address signal.
14. A computer device, comprising a memory and a processor, the memory storing a computer program, wherein the computer program is executed by the processor to implement steps of the method according to claim 12 .
15. A computer-readable storage medium, storing a computer program, wherein the computer program is executed by a processor to implement steps of the method according to claim 12 .