IP Library Granted Patent US 12,401,269
Granted Patent B2
US 12,401,269 · App. 17/858,304 · Granted Aug 26, 2025

Switch circuit for implement a soft start

Inventor: Hiroyuki Kimura (Sendai, JP)
Assignee: WILL SEMICONDUCTOR (SHANGHAI) CO. LTD.
H02M1/36G05F1/468H02M1/08
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,401,269
App. No.
17/858,304
Granted
Aug 26, 2025
Kind
B2
Abstract

A switch circuit includes: a p-channel pass transistor, in which the source is connected to a power source and the drain is connected to a load; and a gate drive circuit, which is connected to the gate of the pass transistor. The gate drive circuit includes: a first transistor, through which a first current is made to flow by turn-on of an on/off signal; and an amplifier, in which a reference voltage corresponding to the first current is input to the negative input end, and a gate voltage of the gate is input to the positive input end, and which controls a gate current from the gate by an output from the output end in a manner that the gate voltage matches the reference voltage, and is capable of setting a maximum current of the output. A soft-on time from turn-on of the on/off signal to turn-on of the pass transistor is set by setting the maximum current according to the gate capacitance of the pass transistor.

Claims (16)

1. A switch circuit, comprising:

a p-channel pass transistor, in which a source is connected to a power source and a drain is connected to a load; and

a gate drive circuit, which is connected to a gate of the pass transistor, wherein

the gate drive circuit comprises:

a first transistor, through which a first current is made to flow by turn-on of an on/off signal; and

an amplifier, in which a reference voltage corresponding to the first current is input to a negative input end, and a gate voltage of the gate of the pass transistor is input to a positive input end, and which controls a gate current from the gate of the pass transistor by an output from the output end of the amplifier in a manner that the gate voltage of the gate of the pass transistor matches the reference voltage, while the gate voltage is higher than the reference voltage, an output current of the amplifier increases, a maximum value of the output current is defined as a maximum current of the output of the amplifier, and

a soft-on time from turn-on of the on/off signal to turn-on of the pass transistor is set by setting the maximum current according to a gate capacitance of the pass transistor.

2. The switch circuit according to claim 1 , further comprising:

a second transistor, through which a second current is made to flow by turn-off of the on/off signal, wherein

a soft-off time from turn-off of the on/off signal to turn-off of the pass transistor is set by passing a current corresponding to the second current as a gate current to the gate.

3. The switch circuit according to claim 1 , further comprising:

a first monitor circuit, which comprises a current mirror passing a current corresponding to the maximum current, and outputs a signal about the soft-on time by the current of the current mirror.

4. The switch circuit according to claim 1 , further comprising:

monitor circuit, which outputs a signal if the gate voltage is nearly 0 V when the pass transistor is fully turned on.

5. The switch circuit according to claim 1 , further comprising:

a third monitor circuit, which outputs a signal when the gate-to-source voltage of the pass transistor is less than a predetermined value.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2022
From: KIMURA, HIROYUKI
To: WILL SEMICONDUCTOR (SHANGHAI) CO. LTD.
Reel/Frame 060427/0976 →
Priority Claims (1)
CN 202210625184.5 · Jun 2, 2022 · national
Continuity (1)
Related Publication 20230396148A1 · Dec 7, 2023
References Cited (16)
US 5698973A · Goerke · 1997 [cited by examiner]
US 6188212B1 · Larson · 2001 [cited by examiner]
US 7948277B2 · Nakatake · 2011 [cited by examiner]
US 8427802B2 · Yoshizawa · 2013 [cited by examiner]
US 9647657B1 · Bryson et al. · 2017 [cited by applicant]
US 9825468B1 · Bryson et al. · 2017 [cited by applicant]
US 10432175B2 · Choi et al. · 2019 [cited by applicant]
US 10868521B2 · Choi et al. · 2020 [cited by applicant]
US 20100052636A1 · Takagi · 2010 [cited by examiner]
US 20100156367A1 · Takagi · 2010 [cited by examiner]
US 20120081092A1 · Pavlin · 2012 [cited by examiner]
US 20130176008A1 · Li · 2013 [cited by examiner]
US 20150311692A1 · Hiyama · 2015 [cited by examiner]
US 20190222201A1 · Wang · 2019 [cited by examiner]
US 20190310675A1 · Araragi · 2019 [cited by examiner]
US 20220308609A1 · Koay · 2022 [cited by examiner]