IP Library › Granted Patent US 12,402,343
Granted Patent B2
US 12,402,343 · App. 17/807,513 · Granted Aug 26, 2025

Work function tuning in semiconductor devices

Inventors: Hsin-Yi Lee (Hsinchu, TW); Sheng-Yung Chang (Hsinchu, TW); Cheng-Lung Hung (Hsinchu, TW); Chi On Chui (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H10D30/024H10D30/6735H10D30/6211H10D62/119
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Quick Facts
Patent No.
US 12,402,343
App. No.
17/807,513
Granted
Aug 26, 2025
Kind
B2
Abstract

The present disclosure describes a method for forming a semiconductor device having a work function metal layer doped with tantalum to mitigate oxygen diffusion and improve device threshold voltage. The method includes forming a gate dielectric layer on a channel structure and forming a work function metal layer on the gate dielectric layer. The gate dielectric layer includes an interfacial layer on the channel structure and a high-k dielectric layer on the interfacial layer. The method further includes doping the work function metal layer and the gate dielectric layer with tantalum.

Claims (39)

1. A method, comprising:

forming a gate dielectric layer on a channel structure, wherein the gate dielectric layer comprises an interfacial layer on the channel structure and a high-k dielectric layer on the interfacial layer;

forming a work function metal layer on the gate dielectric layer; and

diffusing tantalum into the work function metal layer and the gate dielectric layer.

2. The method of claim 1 , wherein doping the work function metal layer and the gate dielectric layer comprises soaking the work function metal layer with a tantalum precursor for about 0.5 second to about 1800 seconds.

3. The method of claim 1 , wherein doping the work function metal layer and the gate dielectric layer comprises forming a tantalum nitride layer on a titanium nitride layer.

4. The method of claim 3 , wherein a ratio of a thickness of the tantalum nitride layer to a thickness of the titanium nitride layer ranges from about 0.1 to about 1.5.

5. The method of claim 1 , further comprising:

forming an additional work function metal layer on the work function metal layer; and

doping the additional work function metal layer with the tantalum.

6. The method of claim 1 , further comprising:

forming a glue layer on the work function metal layer; and

forming a metal fill on the glue layer.

7. The method of claim 1 , wherein doping the work function metal layer and the gate dielectric layer comprises performing the doping at a temperature from about 150° C. to about 550° C.

8. The method of claim 1 , wherein doping the work function metal layer and the gate dielectric layer comprises performing the doping under a pressure from about 0.1 torr to about 50 torr.

9. The method of claim 1 , wherein the work function metal layer is a p-type work function metal comprising titanium nitride, tungsten nitride, tungsten carbon nitride, or titanium silicon nitride.

10. A method, comprising:

forming a gate dielectric layer on a channel structure, wherein the gate dielectric layer comprises an interfacial layer on the channel structure and a high-k dielectric layer on the interfacial layer;

depositing a work function metal layer on the gate dielectric layer with a titanium precursor, a nitrogen precursor, and a tantalum precursor;

diffusing tantalum in the work function metal layer into the gate dielectric layer; and

forming a metal fill on the work function metal layer.

11. The method of claim 10 , wherein depositing the work function metal layer comprises:

delivering the titanium precursor for a first pulse time; and

delivering the tantalum precursor for a second pulse time different from the first pulse time.

12. The method of claim 11 , wherein a ratio of the first pulse time to the second pulse time ranges from about 0.15 to about 10.

13. The method of claim 10 , wherein depositing the work function metal layer comprises performing the deposition at a temperature from about 150° C. to about 550° C.

14. The method of claim 10 , wherein depositing the work function metal layer comprises performing the deposition under a pressure from about 0.1 torr to about 50 torr.

15. A method, comprising:

forming a gate dielectric layer in a gate stack opening, wherein the gate dielectric layer comprises an interfacial layer and a high-k dielectric layer;

forming a work function metal layer on the gate dielectric layer;

diffusing tantalum into the work function metal layer and the gate dielectric layer under a thermal condition; and

depositing a metal fill in the gate stack opening and on the work function layer.

16. The method of claim 15 , wherein forming the work function metal layer comprises soaking the work function metal layer and the high-k dielectric layer with a tantalum precursor for about 0.5 second to about 1800 seconds.

17. The method of claim 16 , wherein the work function metal layer and the high-k dielectric layer are soaked at a temperature from about 150° C. to about 550° C.

18. The method of claim 16 , wherein the work function metal layer and the high-k dielectric layer are soaked under a pressure from about 0.1 torr to about 50 torr.

19. The method of claim 15 , wherein forming the work function metal layer comprises:

forming a titanium nitride layer on the high-k dielectric layer; and

forming a tantalum nitride layer on the titanium nitride layer.

20. The method of claim 19 , wherein a ratio of a thickness of the tantalum nitride layer to a thickness of the titanium nitride layer ranges from about 0.1 to about 1.5.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNEE NAME PREVIOUSLY RECORDED ON REEL 64235 FRAME 786. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded May 7, 2025
From: CHANG, SHENG-YUNG; LEE, HSIN-YI; HUNG, CHENG-LUNG; CHUI, CHI ON
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 072006/0163 →
CORRECTIVE ASSIGNMENT TO CORRECT THE FIRST NAME OF THE SECOND INVENTOR PREVIOUSLY RECORDED AT REEL: 060410 FRAME: 0108. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Apr 20, 2023
From: LEE, HSIN-YI; CHANG, SHENG-YUNG; HUNG, CHENG-LUNG; CHUI, CHI ON
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 064235/0786 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2022
From: LEE, HSIN-YI; CHANG, SEAN; HUNG, CHENG-LUNG; CHUI, CHI ON
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 060410/0108 →
Continuity (2)
Provisional Application 63324851 · Mar 29, 2022
Related Publication 20230317446A1 · Oct 5, 2023
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