IP Library › Granted Patent US 12,402,539
Granted Patent B2
US 12,402,539 · App. 18/361,646 · Granted Aug 26, 2025

STT-MRAM heat sink and magnetic shield structure design for more robust read/write performance

Inventors: Tom Zhong (Saratoga, CA); Jesmin Haq (Milpitas, CA); Zhongjian Teng (Santa Clara, CA)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10N50/80G11C11/161H10B61/00H10N50/01H10N50/10
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,402,539
App. No.
18/361,646
Granted
Aug 26, 2025
Kind
B2
Abstract

An STT-MRAM device incorporating a multiplicity of MTJ junctions is encapsulated so that it dissipates heat produced by repeated read/write processes and is simultaneously shielded from external magnetic fields of neighboring devices. In addition, the encapsulation layers can be structured to reduced top lead stresses that have been shown to affect DR/R and Hc. We provide a device design and its method of fabrication that can simultaneously address all of these problems.

Claims (45)

1. A device comprising:

a first magnetic tunneling junction (MTJ) stack;

a first encapsulation layer disposed on a sidewall surface of the first MTJ stack;

a first magnetic shield layer disposed on the first encapsulation layer along the sidewall surface of the first MTJ stack;

a second encapsulation layer disposed on the first encapsulation layer along the sidewall surface of the first MTJ stack;

a dielectric layer disposed directly on the first encapsulation layer, the magnetic shield layer and the second encapsulation layer such that the dielectric layer physically contacts the first encapsulation layer, the magnetic shield layer and the second encapsulation layer; and

a conductive line disposed over the dielectric layer and electrically coupled to the first MTJ stack.

2. The device of claim 1 , further comprising a second MTJ stack, wherein the first encapsulation layer extends continuously from the first MTJ stack to the second MTJ stack.

3. The device of claim 1 , wherein the first encapsulation layer physically contacts the conductive line.

4. The device of claim 3 , wherein the first magnetic shield layer, the second encapsulation layer and the dielectric layer physically contact the conductive line.

5. The device of claim 1 , wherein the first magnetic shield layer physically contacts the conductive line, the second encapsulation layer, the first encapsulation layer and the first MTJ stack.

6. The device of claim 5 , wherein the magnetic shield layer is positioned between the conductive line and the second encapsulation layer, the first encapsulation layer and the first MTJ stack thereby preventing the second encapsulation layer, the first encapsulation layer and the first MTJ stack from physically contacting the conductive line.

7. The device of claim 1 , wherein the first encapsulation layer includes a dielectric material,

wherein the first magnetic shield layer includes a first metal material, and

wherein the second encapsulation layer includes a second metal material that is different from the first metal material.

8. The device of claim 1 , wherein the second encapsulation layer is a first heat shield layer formed of a different material than the first magnetic shield layer.

9. A device comprising:

a first magnetic tunneling junction (MTJ) stack;

a first encapsulation layer disposed on the first MTJ stack;

a first heat shield layer disposed on the first encapsulation layer;

a first magnetic shield layer disposed on the first encapsulation layer;

a conductive feature disposed directly on the first heat shield layer, the first magnetic shield layer and the first MTJ stack; and

an interlayer dielectric fill layer extending continuously from a bottom surface of the conductive feature to a top surface of the first encapsulation layer, the top surface of the first encapsulation layer facing the bottom surface of the conductive feature.

10. The device of claim 9 , wherein the conductive feature is further disposed directly on the first encapsulation layer.

11. The device of claim 9 , wherein the first heat shield layer is disposed directly on the first encapsulation layer, and

wherein the first magnetic shield layer is disposed directly on the first heat shield layer.

12. The device of claim 9 , wherein the first heat shield layer is disposed directly on the first magnetic shield layer, and

wherein the first magnetic shield layer is disposed directly on the first encapsulation layer.

13. The device of claim 9 , further comprising:

a second MTJ stack spaced apart from the first MTJ stack;

the first encapsulation extending continuously from the first MTJ stack to the second MTJ stack;

a second heat shield layer disposed on the first encapsulation layer that is disposed on the second MTJ stack;

a second magnetic shield layer disposed on the first encapsulation layer that is disposed on the second MTJ stack;

the conductive feature extending continuously from the first MTJ stack to the second MTJ stack.

14. The device of claim 13 , wherein the first heat shield layer is discontinuous with respect to the second shield layer, and

wherein the first magnetic shield layer is discontinuous with respect to the second magnetic shield layer.

15. The device of claim 14 , wherein the interlayer dielectric fill layer interfaces with both the first heat shield layer and the first magnetic shield layer.

16. A device comprising: a first magnetic tunneling junction (MTJ) stack and a second MTJ stack; a first encapsulation layer disposed directly on the first MTJ stack and the second MTJ stack such that the first encapsulation layer extends continuously from the first MTJ stack to the second MTJ stack; a first heat shield layer disposed on the first MTJ stack and a second heat shield layer disposed on the second MTJ stack; a first magnetic shield layer disposed on the first MTJ stack and a second magnetic shield layer disposed on the second MTJ stack; a conductive feature disposed on and interfacing with the first and second heat shield layers, the first and second magnetic shield layers and the first and second MTJ stacks; and a dielectric fill layer extending continuously from a bottom surface of the conductive feature to a top surface of the first encapsulation layer, the top surface of the first encapsulation layer facing the bottom surface of the conductive feature.

17. The device of claim 16 , wherein the dielectric fill layer further extends continuously from the first heat shield layer to the second heat shield layer.

18. The device of claim 16 , wherein the dielectric fill layer further extends continuously from the first magnetic shield layer to the second magnetic shield layer.

19. The device of claim 16 , wherein the first encapsulation layer is formed of a material selected from the group consisting of SiN, SiO 2 , Al 2 O 3 and MgO,

wherein the first heat shield layer is formed of a material selected from the group consisting of Ti, TiN, Cu, Ta, TaN, W, Al and AN, and

wherein the first magnetic shield layer is formed of a material selected from the group consisting of NiFe and CoFe.

20. The device of claim 19 , wherein the second heat shield layer is formed of the same material as the first heat shield layer, and

wherein the second magnetic shield layer is formed of the same material as the first magnetic shield layer.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2023
From: ZHONG, TOM; HAQ, JESMIN; TENG, ZHONGJIAN
To: HEADWAY TECHNOLOGIES, INC.
Reel/Frame 065353/0941 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2023
From: HEADWAY TECHNOLOGIES, INC.
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 065354/0001 →
Continuity (3)
Continuation 17107409 · Nov 30, 2020
Division 15857782 · Dec 29, 2017
Related Publication 20230380298A1 · Nov 23, 2023
References Cited (31)
US 6381094B1 · Gill · 2002 [cited by examiner]
US 7262069B2 · Chung et al. · 2007 [cited by applicant]
US 7829980B2 · Malla et al. · 2010 [cited by applicant]
US 8125057B2 · Bonin et al. · 2012 [cited by applicant]
US 8194436B2 · Fukami et al. · 2012 [cited by applicant]
US 9024399B2 · Guo · 2015 [cited by applicant]
US 9081669B2 · Tadepalli et al. · 2015 [cited by applicant]
US 9502466B1 · Chuang · 2016 [cited by examiner]
US 9911914B1 · Annunziata · 2018 [cited by applicant]
US 9985199B1 · Briggs · 2018 [cited by examiner]
US 20060019431A1 · Kasko · 2006 [cited by examiner]
US 20060273418A1 · Chung et al. · 2006 [cited by applicant]
US 20070058422A1 · Phillips et al. · 2007 [cited by applicant]
US 20140061827A1 · Huang · 2014 [cited by examiner]
US 20150091109A1 · Allinger et al. · 2015 [cited by applicant]
US 20150243883A1 · Swaminathan · 2015 [cited by examiner]
US 20150287910A1 · Lu · 2015 [cited by examiner]
US 20160190432A1 · Shum · 2016 [cited by examiner]
US 20160254209A1 · Oohiraki et al. · 2016 [cited by applicant]
US 20160351792A1 · Jiang · 2016 [cited by applicant]
US 20170186943A1 · Annunziata · 2017 [cited by examiner]
US 20180182809A1 · Liu · 2018 [cited by examiner]
US 20180358545A1 · Sundar · 2018 [cited by examiner]
US 20190207083A1 · Zhong et al. · 2019 [cited by applicant]
DE 102016116301A1 · 2017 [cited by applicant]
DE 102016117034A1 · 2017 [cited by applicant]
KR 20160118386A · 2016 [cited by applicant]
German Patent and Trademark Office Application No. 112018005816.6, German Patent and Trademark Office, Examination search report, dated Jan. 31, 2024, 8 pages. [cited by applicant]
Chatterjee, Subho et al., “Impact of Self-Heating on Reliability of a Spin-Torque-Transfer RAM Cell”, IEEE Transactions on Electron Devices, vol. 59, No. 3, Mar. 2012, pp. 791-799. [cited by applicant]
Wang, You e al., “Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction”, IEEE Transactions on Electron Devices, vol. 63, No. 4, Apr. 2016, pp. 1762-1767. [cited by applicant]
Guo, W. et al., “SPICE modelling of magnetic tunnel junctions written by spin-transfer torque”, HAL archives, HAL Id: hal-00569612, Feb. 25, 2011, 16 pgs. [cited by applicant]