IP Library Granted Patent US 12,405,243
Granted Patent B2
US 12,405,243 · App. 17/940,225 · Granted Sep 2, 2025

Circuitry for analyte measurement

Inventor: John P. Lesso (Edinburgh, GB)
Assignee: Cirrus Logic Inc.
G01N27/4161G01N27/002G01N27/30
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Quick Facts
Patent No.
US 12,405,243
App. No.
17/940,225
Granted
Sep 2, 2025
Kind
B2
Abstract

Circuitry for measuring a characteristic of an electrochemical cell, the electrochemical cell comprising at least one working electrode and a counter electrode, the circuitry comprising: driver circuitry configured to apply a working bias voltage to the at least one working electrode and a counter bias voltage at the counter electrode to produce a first voltage bias between the at least one working electrode and the counter electrode; control circuitry configured to adjust the first voltage bias over a first bias range by varying the working bias voltage and the counter bias voltage.

Claims (33)

1. Circuitry for measuring a characteristic of an electrochemical cell, the electrochemical cell comprising at least one working electrode and a counter electrode, the circuitry comprising:

driver circuitry configured to apply a working bias voltage to the at least one working electrode and a counter bias voltage at the counter electrode to produce a first voltage bias between the at least one working electrode and the counter electrode;

control circuitry configured to adjust the first voltage bias over a first bias range by varying the working bias voltage and the counter bias voltage.

2. Circuitry of claim 1 , wherein the control circuitry is configured to hold the working bias voltage at a fixed midpoint voltage while varying the counter bias voltage between a lower reference voltage and an upper reference voltage of the driver circuitry.

3. Circuitry of claim 2 , wherein the lower reference voltage is a ground reference voltage of the driver circuitry positively offset by a headroom voltage, and wherein the upper reference voltage is a supply voltage of the driver circuitry negatively offset by the headroom voltage.

4. Circuitry of claim 2 , wherein when the first voltage bias is a negative voltage bias, the control circuitry is configured to increase a magnitude of the negative voltage bias by decreasing the counter bias voltage until the counter bias voltage is substantially equal to the lower reference voltage.

5. Circuitry of claim 4 , wherein, when the counter bias voltage reaches the lower reference voltage, the control circuitry is configured to increase the working bias voltage to further increase the magnitude of the negative voltage bias.

6. Circuitry of claim 2 , wherein when the first voltage bias is a positive voltage bias, the control circuitry is configured to increase a magnitude of the positive voltage bias by increasing the counter bias voltage until the counter bias voltage is substantially equal to the upper reference voltage.

7. Circuitry of claim 6 , wherein, when the counter bias voltage reaches the upper reference voltage, the control circuitry is configured to decrease the working bias voltage to further increase the magnitude of the positive voltage bias.

8. Circuitry of claim 1 , wherein the first bias range is between a negative bias voltage and a positive bias voltage.

9. Circuitry of claim 1 , wherein:

during a first time period, the control circuitry is configured to linearly increase the first voltage bias from the negative bias voltage to the positive bias voltage; and

during a second time period, the control circuitry is configured to linearly decrease the first voltage bias from the positive bias voltage to the negative bias voltage.

10. Circuitry of claim 1 , wherein the first voltage bias is modulated by a square wave.

11. Circuitry of claim 10 , wherein the voltage bias is modulated by modulating the working bias voltage and/or the counter bias voltage.

12. Circuitry of claim 1 , comprising:

a transimpedance amplifier (TIA) comprising:

a first input coupled to the working electrode;

a second input configured to receive the working bias voltage;

an output configured to output an output voltage; and

a feedback resistor coupled between the output and the first input.

13. Circuitry of claim 12 , wherein the control circuitry is configured to vary a resistance of the feedback resistor in dependence the working bias voltage.

14. Circuitry of claim 13 , comprising a current source configured to provide an offset current to the first input.

15. Circuitry of claim 12 , further comprising an analog-to-digital converter configured to convert the output voltage into a digital representation of the output voltage.

16. Circuitry of claim 1 , wherein the at least one working electrode comprises a first working electrode and a second working electrode.

17. Circuitry of claim 16 , wherein:

the working bias voltage is applied to the first working electrode;

the first voltage bias is between the first working electrode and the counter electrode;

the driver circuitry is configured to apply a second working bias voltage to the second working electrode to produce a second voltage bias between the second working electrode and the counter electrode; and

the control circuitry is configured to adjust the second voltage bias over a second bias range by varying the second working bias voltage and the counter bias voltage.

18. Circuitry of claim 17 , wherein the control circuitry is configured to adjust the working bias voltage, the second working bias voltage and the counter bias voltage such that a sum of absolute values of the first voltage bias and the second voltage vias is less than a supply voltage of the driver circuitry.

19. An electronic device, comprising the circuitry of claim 1 .

20. The electronic device of claim 19 , wherein the device comprises one of a continuous glucose monitor, a mobile computing device, a laptop computer, a tablet computer, a games console, a remote control device, a home automation controller or a domestic appliance, a toy, a robot, an audio player, a video player, or a mobile telephone, and a smartphone.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 11, 2025
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 071382/0667 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 28, 2022
From: LESSO, JOHN P.
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 061585/0288 →
Continuity (1)
Related Publication 20240085370A1 · Mar 14, 2024
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