Current sensor for power electronic converter
A system having: a power switching circuit providing a drive current to a load, and having: a power source; first and second serially connected switches convert DC power from the power source into AC current to form the drive current, or vice versa; a first high-bandwidth current sensor circuit measures high-side current pulses through the first switch and provides a first analog signal, proportional to the high-side pulses; a second high-bandwidth current sensor circuit measures low-side current pulses through the second switch and provides a second analog signal is proportional to the low-side pulses; a signal processing device coupled to the first and second current sensor circuits performs steps of: converting the first analog signal to a first digital signal and the second analog signal to a second digital signal; and reconstructing the drive current and obtaining its cycle average values from the first and second digital signals.
1. A system, comprising:
a power switching circuit that provides a drive current to a load, the circuit comprising:
a power source; and
first and second serially connected switches that convert DC power from the power source into an AC current to form the drive current, or vice versa;
a first high-bandwidth current sensor circuit that measures a series of high-side current pulses through the first switch and provides a first analog signal that is proportional to the series of high-side pulses;
a second high-bandwidth current sensor circuit that measures a series of low-side current pulses through the second switch and provides a second analog signal that is proportional to the series of low-side pulses;
a signal processing device operationally coupled to the first and second current sensor circuits and is configured to perform steps including:
converting the first analog signal to a first digital signal and the second analog signal to a second digital signal; and
reconstructing the drive current and obtaining its cycle average values from the first and second digital signals.
2. The system of claim 1 , wherein the signal processing device is a digital signal processor (DSP).
3. The system of claim 1 , wherein the first switch operates on a first duty cycle and first switching period and the second switch operates on a second duty cycle and second switching period, and the duty cycles are complementary with the first duty cycle being greater than the second duty cycle.
4. The system of claim 3 , wherein when reconstructing the drive current, the DSP is further configured to perform steps including, in each switching cycle:
sampling the first digital signal at a first midpoint of one of the high-side pulses to obtain the first current sample and first duty cycle; and
sampling the second digital signal at a second midpoint of one of the low-side pulses to obtain the second current sample and second duty cycle,
wherein:
when the first duty cycle is greater than a first threshold, the DSP is configured to generate a first output current for the switching cycle that is equal to the high-side pulse sensed while sampling the first digital signal;
when the second duty cycle is greater than a second threshold, the DSP is configured to generate a second output current for the switching cycle that is equal to the low-side pulse sensed while sampling the second digital signal; and
when the first duty cycle is not greater than the first threshold and the second duty cycle is not greater than the second threshold, the DSP is configured to generate a third output current for the switching cycle that is a sum of the high-side pulse and the low-side pulse that are sensed while sampling the first and second digital signals.
5. The system of claim 4 , wherein the first and second thresholds are the same as each other.
6. The system of claim 4 , wherein the first and second thresholds are 0.5.
7. The system of claim 4 , wherein:
the first midpoint of the high-side pulse occurs at: 0.5*DC1*P1 where DC1 is the first duty cycle and P1 is the first switching period; and
the second midpoint of the low-side pulse occurs at: 0.5*DC2*P2 where D2 is the second duty cycle and P2 is the second switching period.
8. The system of claim 3 , wherein the DSP includes a first analog to digital converter (ADC) that converts the first analog signal to the first digital signal and a second ADC that converts the second analog signal to the second digital signal.
9. The system of claim 3 , further comprising:
a load branch extending from a first end to a second end, wherein the first end is connected to the power switching circuit between the first and the second switches and the second end is connected to a load.
10. The system of claim 9 , including an inductor disposed on the load branch, between the first and second ends.
11. The system of claim 9 , wherein the load is a motor.
12. The system of claim 2 , wherein the first switch is a first field-effect transistor (FET) having a first drain-source connection and the second switch is a second field-effect transistor (FET) having a second drain-source connection.
13. The system of claim 12 , wherein the first and second FETs are first and second MOSFETS.
14. The system of claim 2 , wherein the first current sensor circuit includes a first Rogowski coil wound about the first drain-source connection and the second current sensor circuit includes a second Rogowski coil wound about the second drain-source connection.
15. The system of claim 2 , wherein the first current sensor circuit includes a first integration circuit, and the second current sensor circuit includes a second integration circuit.