Matrix transpose and multiply
Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.
1. A processor, comprising:
a plurality of registers to store a plurality of packed data elements including a first plurality of packed data elements of a first source matrix tile and a second plurality of packed data elements of a second source matrix tile, the first and second source matrix tiles comprising respective portions of a first source matrix and a second source matrix, and wherein each packed data element of the plurality of packed data elements has an element width;
a decoder to decode one or more instructions, at least one instruction of the one or more instructions including an opcode field configured to specify an opcode, a first source operand configured to indicate the first plurality of packed data elements, a second source operand configured to indicate the second plurality of packed data elements, and a destination operand configured to indicate a result matrix tile;
execution circuitry, in response to the one or more instructions, to transpose the first source matrix tile in accordance with a granularity equal to the element width to generate a first transposed source matrix tile comprising the first plurality of packed data elements and to multiply the first transposed source matrix tile and the second source matrix tile, the execution circuitry comprising:
a plurality of multipliers to multiply data elements of the first transposed source matrix tile and corresponding data elements of the second source matrix tile to produce a corresponding plurality of products; and
one or more accumulators to add groups of the products to generate corresponding result data elements in the result matrix tile.
2. The processor of claim 1 , wherein to transpose the first source matrix tile, the execution circuitry is to transform each row of the first source matrix tile to a column of the first transposed source matrix tile.
3. The processor of claim 2 , wherein each column of the first transposed source matrix tile has a width equal to the element width.
4. The processor of claim 3 , wherein the element width comprises an 8-bit width or a 16-bit width and a result element width of each of the result data elements comprises a 32-bit width.
5. The processor of claim 4 , wherein the first and second plurality of packed data elements comprise 16-bit floating point data elements and each of the result data elements comprise single-precision floating point data elements.
6. The processor of claim 5 , wherein the 16-bit floating point data elements comprise bfloat16 data elements.
7. The processor of claim 1 , further comprising:
a scheduler to schedule the one or more instructions for execution on the execution circuitry.
8. A method comprising:
storing in a plurality of registers a plurality of packed data elements including a first plurality of packed data elements of a first source matrix tile and a second plurality of packed data elements of a second source matrix tile, the first and second source matrix tiles comprising respective portions of a first source matrix and a second source matrix, and wherein each packed data element of the plurality of packed data elements has an element width;
decoding one or more instructions, at least one instruction of the one or more instructions including an opcode field configured to specify an opcode, a first source operand configured to indicate the first plurality of packed data elements, a second source operand configured to indicate the second plurality of packed data elements, and a destination operand configured to indicate a result matrix tile;
transposing, in response to the one or more instructions, the first source matrix tile in accordance with a granularity equal to the element width to generate a first transposed source matrix tile comprising the first plurality of packed data elements and to multiply the first transposed source matrix tile and the second source matrix tile, wherein multiplying the first transposed source matrix tile and the second source matrix tile comprises:
multiplying data elements of the first transposed source matrix tile and corresponding data elements of the second source matrix tile to produce a corresponding plurality of products; and
adding groups of the products to generate corresponding result data elements in the result matrix tile.
9. The method of claim 8 , wherein transposing the first source matrix tile comprises transforming each row of the first source matrix tile to a column of the first transposed source matrix tile.
10. The method of claim 9 , wherein each column of the first transposed source matrix tile has a width equal to the element width.
11. The method of claim 10 , wherein the element width comprises an 8-bit width or a 16-bit width and a result element width of each of the result data elements comprises a 32-bit width.
12. The method of claim 11 , wherein the first and second plurality of packed data elements comprise 16-bit floating point data elements and each of the result data elements comprise single-precision floating point data elements.
13. The method of claim 12 , wherein the 16-bit floating point data elements comprise bfloat16 data elements.
14. The method of claim 8 , further comprising:
scheduling the one or more instructions for execution on the execution circuitry.
15. A non-transitory machine-readable medium containing instructions which, when executed by a processor, are to cause the processor to respond by:
storing in a plurality of registers a plurality of packed data elements including a first plurality of packed data elements of a first source matrix tile and a second plurality of packed data elements of a second source matrix tile, the first and second source matrix tiles comprising respective portions of a first source matrix and a second source matrix, and wherein each packed data element of the plurality of packed data elements has an element width;
decoding one or more instructions, at least one instruction of the one or more instructions including an opcode field configured to specify an opcode, a first source operand configured to indicate the first plurality of packed data elements, a second source operand configured to indicate the second plurality of packed data elements, and a destination operand configured to indicate a result matrix tile;
transposing, in response to the one or more instructions, the first source matrix tile in accordance with a granularity equal to the element width to generate a first transposed source matrix tile comprising the first plurality of packed data elements and to multiply the first transposed source matrix tile and the second source matrix tile, wherein multiplying the first transposed source matrix tile and the second source matrix tile comprises:
multiplying data elements of the first transposed source matrix tile and corresponding data elements of the second source matrix tile to produce a corresponding plurality of products; and
adding groups of the products to generate corresponding result data elements in the result matrix tile.
16. The machine-readable medium of claim 15 , wherein transposing the first source matrix tile comprises transforming each row of the first source matrix tile to a column of the first transposed source matrix tile.
17. The machine-readable medium of claim 16 , wherein each column of the first transposed source matrix tile has a width equal to the element width.
18. The machine-readable medium of claim 17 , wherein the element width comprises an 8-bit width or a 16-bit width and a result element width of each of the result data elements comprises a 32-bit width.
19. The machine-readable medium of claim 18 , wherein the first and second plurality of packed data elements comprise 16-bit floating point data elements and each of the result data elements comprise single-precision floating point data elements.
20. The machine-readable medium of claim 19 , wherein the 16-bit floating point data elements comprise bfloat16 data elements.