Method and system for efficient hardware mapping of generative giant artificial intelligence model
Provided is a method and system for efficient hardware mapping of a generative giant artificial intelligence model. A hardware mapping method may include receiving, by at least one processor, model software and sequentially performing, by the at least one processor, source code level simulation, instruction level simulation, and register transfer level simulation for the model software.
1. A hardware mapping method of a computer device comprising at least one processor, the hardware mapping method comprising:
receiving, by the at least one processor, model software of a generative artificial intelligence model including a large language model (LLM);
receiving, by the at least one processor, information on an existing hardware structure; and
sequentially performing, by the at least one processor, source code level simulation, instruction level simulation, and register transfer level simulation for the model software,
wherein the performing comprises:
cross-verifying an instruction written with the source code level simulation through the instruction level simulation,
determining whether implementation of the model software is possible with the existing hardware structure after performing the source code level simulation and performing the cross-verifying before performing the register transfer level simulation;
adding a hardware module to the existing hardware structure when the implementation is impossible; and
reperforming the instruction level simulation for verifying the instruction,
wherein the adding and the reperforming are repeated until the implementation of the model software is determined to be possible with the hardware structure including the added hardware module, and
wherein the performing further comprises:
writing a module-level test case for each instruction cross-verified through the source code level simulation and the instruction level simulation; and
verifying at least one of the written test cases through the register transfer level simulation.
2. The hardware mapping method of claim 1 , wherein the verifying comprises performing cross-verification through the register transfer level simulation and the instruction level simulation.
3. The hardware mapping method of claim 1 , wherein the performing comprises:
processing cross-verification through the source code level simulation and the instruction level simulation using a graphics processing unit (GPU); and
processing multithread loading of a file of the model software for the register transfer level simulation.
4. The hardware mapping method of claim 3 , wherein the processing of the multithread loading comprises separating the file of the model software for each channel of a memory and loading the same to the memory through multithreading.
5. A non-transitory computer-readable recording medium storing a program to execute the method of claim 1 on the computer device.
6. The hardware mapping method of claim 1 , wherein the receiving comprises a plurality of model software components including the model software, each of the model software components being a generative artificial intelligence model including a large language model (LLM), and
wherein the sequentially performing comprises sequentially performing the source code level simulation, the instruction level simulation, and the register transfer level simulation for each of the model software components in a pipelined manner such that the model software components are processed in parallel for hardware mapping thereto.
7. A computer device comprising:
at least one processor configured to execute computer-readable instructions,
wherein the at least one processor is configured to,
receive model software of a generative artificial intelligence model including a large language model (LLM), and
sequentially perform source code level simulation, instruction level simulation, and register transfer level simulation for the model software,
wherein the at least one processor is configured to
cross-verify an instruction written with the source code level simulation through the instruction level simulation,
determine whether implementation of the model software is possible with the existing hardware structure after performing the source code level simulation and performing the cross-verifying before performing the register transfer level simulation,
add a hardware module to the existing hardware structure when the implementation is impossible, and
reperform the instruction level simulation for verifying the instruction,
wherein the adding and the reperforming are repeated until the implementation of the model software is determined to be possible with the hardware structure including the added hardware module,
wherein the at least one processor is configured to
write a module-level test case for each instruction cross-verified through the source code level simulation and the instruction level simulation, and
verify at least one of the written test cases through the register transfer level simulation.
8. The computer device of claim 7 , wherein, to verify at least one of the written test cases, the at least one processor is configured to perform cross-verification through the register transfer level simulation and the instruction level simulation.
9. The computer device of claim 7 , wherein the at least one processor is configured to,
process cross-verification through the source code level simulation and the instruction level simulation using a graphics processing unit (GPU) included in the at least one processor, and
process multithread loading of a file of the model software for the register transfer level simulation using a central processing unit (CPU) included in the at least one processor.