IP Library › Granted Patent US 12,405,826
Granted Patent B2
US 12,405,826 · App. 17/446,427 · Granted Sep 2, 2025

Reservation mechanism for nodes with phase constraints

Inventors: Brendan M. Wong (Beaumont, TX); Bradley Donald Bingham (Austin, TX)
Assignee: International Business Machines Corporation
G06F9/5027G06F13/368H04L12/427
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,405,826
App. No.
17/446,427
Granted
Sep 2, 2025
Kind
B2
Abstract

A computer chip, a method, and computer program product for providing phase reservations between processing nodes. A computer chip includes a plurality of processing nodes interconnected in an on-chip data transfer network configured in a circular topology. The processing nodes include reservation mechanisms managing reservations made by processing nodes with phase constraints. The reservation policy allows the processing nodes to make a reservation, for a given phase, in any phase window, only once per reservation window. A reservation window can be a bounded amount of time for when a node is guaranteed an opportunity to transmit at least one message. The reservation policy also prevents the processing nodes from making more than one reservation in a phase window. Once a reservation is granted, the corresponding message may progress on the bus unimpeded. Requestors attempting to transmit messages are blocked until the message is transmitted.

Claims (36)

1. A computer chip comprising a data transfer network, the data transfer network comprising:

a plurality of buses configured on the computer chip, wherein the plurality of buses are configured in a circular topology network, wherein each bus of the plurality of buses provides a plurality of slots for transmission of information;

a plurality of processing nodes, wherein each processing node of the plurality of processing nodes is coupled to the plurality of buses, wherein one or more source processing nodes of the plurality of processing nodes routes data to a destination processing node of the plurality of processing nodes according to phase-based arbitration constraints that regulate transmission of information on the plurality of buses to the destination processing node only on a cycle that matches a phase window in which the destination processing node is allowed to receive the information on the plurality of buses; and

a plurality of reservation mechanisms, wherein each of the plurality of reservation mechanisms is coupled to a corresponding processing node of the plurality of processing nodes to manage reservations between the plurality of processing nodes that allow communication to occur between the plurality of processing nodes within a predetermined amount of time, wherein each of the plurality of reservation mechanisms applies on a corresponding processing node a reservation policy for transmitting information on a bus of the plurality of buses according to the phase-based arbitration constraints when a processing node satisfies a starvation condition, wherein the starvation condition is a predetermined amount of time the processing node is unable to transmit a message, wherein the reservation policy defines a reservation window having a number of cycles for transmitting information to the destination processing node, wherein the reservation window is determined in part by a most restrictive phase constraint of a processing node in the plurality of processing nodes, wherein the reservation policy resets at an end of the reservation window.

2. The computer chip of claim 1 , wherein the reservation policy allows the plurality of processing nodes to make a reservation for a phase in a phase window only once in a reservation window.

3. The computer chip of claim 1 , wherein the reservation provides a reserved slot on a bus of the plurality of buses by blocking other messages on the bus.

4. The computer chip of claim 1 , wherein the reservation allows each processing node to request a reservation corresponding to a phase-policy based arbitration constraint of the processing node at least once in the reservation window.

5. The computer chip of claim 1 , wherein the reservations reserve data transfer messages between the plurality of processing nodes.

6. The computer chip of claim 1 , wherein the plurality of buses include a communications bus and a reservation bus.

7. The computer chip of claim 1 , wherein the reservation mechanisms maintain a local state of previous reservations made within a reservation window to maintain adherence with the reservation policy.

8. A computer-implemented method of managing reservations between a plurality of processing nodes with phase-based arbitration constraints, where each processing node of the plurality of processing nodes includes an arbiter, the computer-implemented method comprising:

requesting, by a source processing node of the plurality of processing nodes to an arbiter of the source processing node, transmission of a message from the source processing node of the plurality of processing nodes to a destination processing node of the plurality of processing nodes,

wherein the source processing node and the destination processing node are connected within a circular topology network, wherein the circular topology network comprises a plurality of buses, wherein each bus of the plurality of buses provides a plurality of slots for transmission of information,

wherein processing nodes of the plurality of processing nodes are configured with the phase-based arbitration constraints which regulate transmission of information on the plurality of buses to the destination processing node only on a cycle that matches a phase window in which the destination processing node is allowed to receive the information on the plurality of buses;

determining, by the arbiter in the source processing node, that the source processing node has met a starvation condition when requesting transmission of the message, wherein the starvation condition is a predetermined amount of time the source processing node is unable to transmit a message,

wherein a reservation policy for transmitting information on a communication bus of the plurality of buses according to the phase-based arbitration constraints is applied to the plurality of processing nodes when a processing node satisfies the starvation condition, the reservation policy defining a reservation window having a number of cycles that is determined in part by a most restrictive phase constraint of a processing node in the plurality of processing nodes, and the reservation policy resets at an end of the reservation window;

placing, by the source processing node, a reservation for a given phase in a phase window onto a reservation bus of the plurality of buses, wherein the reservation adheres to the reservation policy restricting reservations between the plurality of processing nodes on the network, wherein the reservation is placed in a reserved slot allowed by the phase-based arbitration constraints of the destination processing node;

observing, by the source processing node, a return corresponding to the reservation on the reservation bus providing the reserved slot for the message on the communication bus of the plurality of buses; and

transmitting, by the source processing node, the message to the destination processing node in the reserved slot generated by the reservation.

9. The computer-implemented method of claim 8 , wherein the reservation policy allows the plurality processing nodes to make a reservation for a given phase in a phase window only once per a reservation window.

10. The computer-implemented method of claim 8 , wherein the reservation provides a reserved slot on a bus of the plurality of buses by blocking other messages on the bus.

11. The computer-implemented method of claim 8 , wherein the reservation policy allows each processing node to request a reservation that corresponds to a phase-based arbitration constraint of the processing node at least once in the reservation window.

12. The computer-implemented method of claim 8 , wherein the source processing node maintains a local state of previous reservations made within a reservation window to maintain adherence with the reservation policy.

13. A computer program product including at least one computer readable storage medium having computer executable instructions for managing reservations between a plurality of processing nodes with phase-based arbitration constraints, where each processing node includes an arbiter, that when executed by at least one computer cause the at least one computer to execute the instructions to:

requesting, by a source processing node of a plurality of processing nodes to an arbiter of the source processing node, transmission of a message from the source processing node of the plurality of processing nodes to a destination processing node of the plurality of processing nodes,

wherein the source processing node and the destination processing node are connected within a circular topology network, wherein circular topology network comprises a plurality of buses, wherein each bus of the plurality of buses provides a plurality of slots for transmission of information,

wherein processing nodes of the plurality of processing nodes are configured with phase-based arbitration constraints that regulate transmission information on the plurality of buses to the destination processing node only on a cycle that matches a phase window in which the destination processing node is allowed to receive the information on the plurality of buses;

determining, by the arbiter in the processing node, that the source processing node has met a starvation condition when requesting transmission of the message, wherein the starvation condition is a predetermined amount of time the source processing node is unable to transmit a message,

wherein a reservation policy for transmitting information on a communication bus of the plurality of buses according to the phase-based arbitration constraints is applied to the plurality of processing nodes when a processing node satisfies the starvation condition, the reservation policy defining a reservation window having a number of cycles that is determined in part by a most restrictive phase constraint of a processing node in the plurality of processing nodes, and the reservation policy resets at an end of the reservation window;

placing, by the source processing node, a reservation for a given phase in a phase window onto a reservation bus of the plurality of buses, wherein the reservation adheres to the reservation policy restricting reservations between the plurality of processing nodes on the network, wherein the reservation is placed in a reserved slot allowed by the phase-based arbitration constraints of the destination processing node;

observing, by the source processing node, a return corresponding to the reservation on the reservation bus providing the reserved slot for the message on the communication bus of the plurality of buses; and

transmitting, by the source processing node, the message to the destination processing node in the reserved slot generated by the reservation.

14. The computer program product of claim 13 , wherein the reservation policy allows the plurality processing nodes to request a reservation for a phase in a phase window only once per a reservation window.

15. The computer program product of claim 13 , wherein the reservation provides a reserved slot on a bus of the plurality of buses by blocking other messages on the bus.

16. The computer program product of claim 13 , wherein the reservation policy allows each processing node to request a reservation that corresponds to a phase-based arbitration constraint of the processing node at least once in the reservation window.

17. The computer program product of claim 13 , wherein the source processing node maintains a local state of previous reservations made with the reservation policy.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2021
From: WONG, BRENDAN M.; BINGHAM, BRADLEY DONALD
To: INTERNATIONAL BUSINESS MACHINES CORPORATION
Reel/Frame 057332/0357 →
Continuity (1)
Related Publication 20230068740A1 · Mar 2, 2023
References Cited (87)
US 4907224A · Scoles · 1990 [cited by applicant]
US 5131085A · Eikill · 1992 [cited by applicant]
US 5185737A · Nassehi · 1993 [cited by applicant]
US 5908468A · Hartmann · 1999 [cited by applicant]
US 5953510A · Herzl · 1999 [cited by applicant]
US 6516368B1 · Arimilli · 2003 [cited by applicant]
US 6848003B1 · Arimilli · 2005 [cited by applicant]
US 7493417B2 · Arimilli · 2009 [cited by applicant]
US 7627738B2 · Chung · 2009 [cited by applicant]
US 7650076B2 · Su · 2010 [cited by applicant]
US 7747771B1 · Shah · 2010 [cited by applicant]
US 7751426B2 · Hillyard · 2010 [cited by applicant]
US 7870337B2 · Bell, Jr. · 2011 [cited by applicant]
US 8560776B2 · Drapala · 2013 [cited by applicant]
US 9178827B2 · Kaplan · 2015 [cited by applicant]
US 9665294B2 · Povzner · 2017 [cited by applicant]
US 9979668B2 · Chen · 2018 [cited by applicant]
US 10496333B2 · Yang · 2019 [cited by applicant]
US 10705985B1 · Pollak · 2020 [cited by applicant]
US 10764185B2 · Marshall · 2020 [cited by applicant]
US 10855389B1 · Roggendorf · 2020 [cited by applicant]
US 11580058B1 · Marino · 2023 [cited by examiner]
US 11593134B2 · Wang · 2023 [cited by applicant]
US 20030033555A1 · Joyner · 2003 [cited by applicant]
US 20030202530A1 · Jenkins · 2003 [cited by applicant]
US 20030212812A1 · Wang · 2003 [cited by examiner]
US 20040210696A1 · Meyer · 2004 [cited by applicant]
US 20040230751A1 · Blake · 2004 [cited by applicant]
US 20050080941A1 · Moll · 2005 [cited by applicant]
US 20060045120A1 · Mattina · 2006 [cited by examiner]
US 20060104296A1 · Rodrigo · 2006 [cited by examiner]
US 20070297441A1 · Heil · 2007 [cited by examiner]
US 20080034054A1 · Stehley · 2008 [cited by examiner]
US 20080104245A1 · Romero · 2008 [cited by applicant]
US 20080159176A1 · Heil · 2008 [cited by examiner]
US 20090067428A1 · Balandin · 2009 [cited by applicant]
US 20090252172A1 · Hare · 2009 [cited by examiner]
US 20090327651A1 · Cargnoni · 2009 [cited by applicant]
US 20100095036A1 · Mittal · 2010 [cited by examiner]
US 20100299734A1 · Lynch · 2010 [cited by applicant]
US 20120030448A1 · Lieske · 2012 [cited by applicant]
US 20120089984A1 · Adar · 2012 [cited by applicant]
US 20120102561A1 · Butt · 2012 [cited by applicant]
US 20120159087A1 · Cox · 2012 [cited by applicant]
US 20140082238A1 · Ahmad · 2014 [cited by applicant]
US 20140185451A1 · Yip · 2014 [cited by applicant]
US 20140233575A1 · Xie · 2014 [cited by examiner]
US 20140280700A1 · Maitland · 2014 [cited by applicant]
US 20140372646A1 · Salisbury · 2014 [cited by applicant]
US 20150009906A1 · Dore · 2015 [cited by examiner]
US 20150255126A1 · Khwa · 2015 [cited by applicant]
US 20160070593A1 · Harris · 2016 [cited by applicant]
US 20170099213A1 · Bruckner · 2017 [cited by examiner]
US 20180324827A1 · Abraham · 2018 [cited by applicant]
US 20190018776A1 · Sato · 2019 [cited by applicant]
US 20190042486A1 · Guthrie · 2019 [cited by applicant]
US 20200042449A1 · Marino · 2020 [cited by applicant]
US 20200279250A1 · Good · 2020 [cited by applicant]
US 20200296083A1 · Chennuri · 2020 [cited by applicant]
US 20210037544A1 · Andrews · 2021 [cited by applicant]
US 20220308877A1 · Maiyuran · 2022 [cited by applicant]
US 20220342542A1 · Alkalay · 2022 [cited by applicant]
US 20230061266A1 · Marino · 2023 [cited by applicant]
US 20230064969A1 · Wong · 2023 [cited by applicant]
US 20230118362A1 · Marino · 2023 [cited by applicant]
EP 0465027A2 · 1992 [cited by applicant]
WO 9103898A1 · 1991 [cited by applicant]
WO 2023031015A1 · 2023 [cited by applicant]
WO 2023031016A1 · 2023 [cited by applicant]
Bianchi, Giuseppe & Bonola, Marco & Bruschi, Valerio & Petrucci, Luca & Pontarelli, S.. (2017). Implementing a Per-Flow Token Bucket Using Open Packet Processor. 251-262. 10.1007/978-3-319-67639-5_18, https://www.resear… [cited by applicant]
Chakrabarti, Ayan, Roch Gu'erin, Chenyang Lu and Jiangnan Liu. “Real-Time Edge Classification: Optimal Offloading under Token Bucket Constraints.” ArXiv abs/2010.13737 (2020): n. pag., https://arxiv.org/abs/2010.13737. [cited by applicant]
Coté, E. A., & Manjikian, N. (2007). Implementation of coarse-grain coherence tracking support in ring-based multiprocessors. A thesis submitted to the Department of Electrical and Computer Engineering, Queen's Universi… [cited by applicant]
Disclosed Anonymously, “Fairness circuit for automic read-modify-write operations on multiprocessor systems,” IP.com Electronic Publication Date: Nov. 6, 2018, IP.com Electronic Publication Date: Nov. 6, 2018, https://i… [cited by applicant]
Disclosed Anonymously, “Reserved slots in PowerBus attached units for off-chip traffic to reduce link congestion due to retries,” IP.com Electronic Publication Date: Jan. 30, 2015, IP.com No. IPCOM000240448D, https://pr… [cited by applicant]
Eynde, Jeremy Van Den. “Token Bucket-Based Throughput Constraining in Cross-Layer Schedulers.” ArXiv.org, Nov. 27, 2019, arxiv.org/abs/1911.12079. [cited by applicant]
Itamar Elhanany and Dan Sadot, A Contention-Free Tbit/sec Packet-Switching Architecture for ATM over WDM Networks, IEICE Trans. Commun., vol. E83-B, No. 2 Feb. 2000, https://www.researchgate.net/publication/2824295_A_Co… [cited by applicant]
Li, F.. “Local and Global QoS-aware Token Bucket Parameters Determination for Traffic Conditioning in 3rd Generation Wireless Networks.” (2002), http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.385.8754. [cited by applicant]
List of IBM Patents or Patent Applications Treated as Related. [cited by applicant]
M. Hamdi, “ORMA: a high-performance MAC protocol for fiber-optic LANs/MANs,” in IEEE Communications Magazine, vol. 35, No. 3, pp. 110-119, Mar. 1997, doi: 10.1109/35.581315. [cited by applicant]
Marty, M. R., & Hill, M. D. (2006, December). Coherence ordering for ring-based chip multiprocessors. In 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06) (pp. 309-320). IEEE. [cited by applicant]
Orlando Moreira, Jacob Jan-David Mol, and Marco Bekooij. 2007. Online resource management in a multiprocessor with a network-on-chip. In <i>Proceedings of the 2007 ACM symposium on Applied computing</i> (<i>SAC '07</i>)… [cited by applicant]
Vranesic, Z. G., Brown, S., Stumm, M., Caranci, S., Grbic, A., Grindley, R., . . . & Srbljic, S. (1995). The NUMAchine multiprocessor. University of Toronto. Computer Systems Research Institute. [cited by applicant]
Y. Peng, Q. Liu and P. Varman, “Scalable QoS for Distributed Storage Clusters using Dynamic Token Allocation,” 2019 35th Symposium on Mass Storage Systems and Technologies (MSST), 2019, pp. 14-27, doi: 10.1109/MSST.2019… [cited by applicant]
PCT/EP2022/073700 Notification of Transmittal of International Search Report and the Written Opinion of the International Searching Authority or the Declaration. Mailed Feb. 2, 2023. 23 pgs. [cited by applicant]
List of IBM Patents or Patent Applications Treated as Related, signed Aug. 30, 2022 (2 pgs). [cited by applicant]
PCT/EP2022/073700 Form PC/ISA/206—Annex to Form PCT/ISA/206 Communication Relating to the Results of the Partial International Search. Mailed Nov. 30, 2022. 14 pages. [cited by applicant]
PCT/EP2022/073698. International Search Report and Written Opinion mailed Nov. 9, 2022. [cited by applicant]