IP Library › Granted Patent US 12,405,885
Granted Patent B2
US 12,405,885 · App. 17/598,190 · Granted Sep 2, 2025

Avoidance of garbage collection in high performance memory management systems

Inventors: Yao Zu Dong (Shanghai, CN); Qiming Shi (Shanghai, CN); Chao Xie (Shanghai, CN); Bin Yang (Shanghai, CN); Zhen Zhou (Shanghai, CN)
Assignee: INTEL CORPORATION
G06F12/0253G06F9/5016G06F9/5022G06F9/544G06F2212/1016G06F2212/7205
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,405,885
App. No.
17/598,190
Granted
Sep 2, 2025
Kind
B2
Abstract

Systems, apparatuses and methods may provide for technology that detects a creation of a thread, dedicates a memory region to objects associated with the thread, and conducts a reclamation of the memory region in response to a termination of the thread. In one example, the memory region is a heap region and the reclamation bypasses at least a pause phase and a copy phase of a garbage collection process with respect to the heap region.

Claims (77)

1. A performance-enhanced computing system comprising:

a display;

a processor coupled to the display; and

a memory coupled to the processor, the memory including a set of executable program instructions, which when executed by the processor, cause the computing system to:

detect a creation of a first thread,

activate thread based allocation for the first thread based on the first thread being associated with user interface activity,

switch to a normal allocation mode from the thread based allocation for a third thread based on the third thread not being associated with the user interface activity,

dedicate a first memory region to objects associated with only the first thread to bypass a storage of objects associated with a second thread into the first memory region based on the thread based allocation being activated for the first thread,

dedicate a second memory region to the objects associated with the second thread,

execute the normal allocation mode for objects associated with the third thread to store the objects of the third thread in a shared space based on the third thread being switched to the normal allocation mode, and

conduct a first reclamation of the first memory region in response to a termination of the first thread.

2. The computing system of claim 1 , wherein the first memory region is a heap region and the first reclamation is to bypass a pause phase and a copy phase of a garbage collection process with respect to the heap region.

3. The computing system of claim 1 , wherein to dedicate the first memory region to the objects associated with the first thread, the executable program instructions, when executed, cause the computing system to:

map the first thread to the first memory region.

4. The computing system of claim 3 , wherein the executable program instructions, when executed, cause the computing system to:

deactivate the thread based allocation in response to the termination of the first thread; and

unmap the first thread from the first memory region.

5. The computing system of claim 1 , wherein the executable program instructions, when executed, cause the computing system to:

dedicate a third memory region to the objects associated with the first thread in response to a determination that the first memory region is full; and

conduct a second reclamation of the third memory region in response to the termination of the first thread.

6. The computing system of claim 1 , wherein the first and second threads are to correspond to the user interface activity, and wherein the display is to visually present information associated with the user interface activity.

7. A semiconductor apparatus comprising:

one or more substrates; and

logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:

detect a creation of a first thread;

activate thread based allocation for the first thread based on the first thread being associated with user interface activity;

switch to a normal allocation mode from the thread based allocation for a third thread based on the third thread not being associated with the user interface activity;

dedicate a first memory region to objects associated with only the first thread to bypass a storage of objects associated with a second thread into the first memory region based on the thread based allocation being activated for the first thread;

dedicate a second memory region to the objects associated with the second thread;

execute the normal allocation mode for objects associated with the third thread to store the objects of the third thread in a shared space based on the third thread being switched to the normal allocation mode; and

conduct a first reclamation of the first memory region in response to a termination of the first thread.

8. The apparatus of claim 7 , wherein the first memory region is a heap region and the first reclamation is to bypass a pause phase and a copy phase of a garbage collection process with respect to the heap region.

9. The apparatus of claim 7 , wherein to dedicate the first memory region to the objects associated with the first thread, the logic coupled to the one or more substrates is to:

map the first thread to the first memory region.

10. The apparatus of claim 9 , wherein the logic coupled to the one or more substrates is to:

deactivate the thread based allocation in response to the termination of the first thread; and

unmap the first thread from the first memory region.

11. The apparatus of claim 7 , wherein the logic coupled to the one or more substrates is to:

dedicate a third memory region to the objects associated with the first thread in response to a determination that the first memory region is full; and

conduct a second reclamation of the third memory region in response to the termination of the first thread.

12. The apparatus of claim 7 , wherein the first and second threads are to correspond to the user interface activity.

13. At least one non-transitory computer readable storage medium comprising a set of executable program instructions, which when executed by a computing system, cause the computing system to:

detect a creation of a first thread;

activate thread based allocation for the first thread based on the first thread being associated with user interface activity;

switch to a normal allocation mode from the thread based allocation for a third thread based on the third thread not being associated with the user interface activity;

dedicate a first memory region to objects associated with only the first thread to bypass a storage of objects associated with a second thread into the first memory region based on the thread based allocation being activated for the first thread;

dedicate a second memory region to the objects associated with the second thread;

execute the normal allocation mode for objects associated with the third thread to store the objects of the third thread in a shared space based on the third thread being switched to the normal allocation mode; and

conduct a first reclamation of the first memory region in response to a termination of the first thread.

14. The at least one non-transitory computer readable storage medium of claim 13 , wherein the first memory region is a heap region and the first reclamation is to bypass a pause phase and a copy phase of a garbage collection process with respect to the heap region.

15. The at least one non-transitory computer readable storage medium of claim 13 , wherein to dedicate the first memory region to the objects associated with the first thread, the executable program instructions, when executed, cause the computing system to:

map the first thread to the first memory region.

16. The at least one non-transitory computer readable storage medium of claim 15 , wherein the executable program instructions, when executed, cause the computing system to:

deactivate the thread based allocation in response to the termination of the first thread; and

unmap the first thread from the first memory region.

17. The at least one non-transitory computer readable storage medium of claim 13 , wherein the executable program instructions, when executed, cause the computing system to:

dedicate a third memory region to the objects associated with the first thread in response to a determination that the first memory region is full; and

conduct a second reclamation of the third memory region in response to the termination of the first thread.

18. The at least one non-transitory computer readable storage medium of claim 13 , wherein the first and second threads are to correspond to the user interface activity.

19. A method comprising:

detecting a creation of a first thread;

activating thread based allocation for the first thread based on the first thread being associated with user interface activity;

switching to a normal allocation mode from the thread based allocation for a third thread based on the third thread not being associated with the user interface activity;

dedicating a first memory region to objects associated only with the first thread to bypass a storage of objects associated with a second thread into the first memory region based on the thread based allocation being activated for the first thread;

dedicating a second memory region to the objects associated with the second thread;

executing the normal allocation mode for objects associated with the third thread to store the objects of the third thread in a shared space based on the third thread being switched to the normal allocation mode; and

conducting a first reclamation of the first memory region in response to a termination of the first thread.

20. The method of claim 19 , wherein the first memory region is a heap region and the first reclamation bypasses a pause phase and a copy phase of a garbage collection process with respect to the heap region.

21. The method of claim 19 , wherein dedicating the first memory region to the objects associated with the first thread includes:

mapping the first thread to the first memory region.

22. The method of claim 21 , further including:

deactivating the thread based allocation in response to the termination of the first thread; and

unmapping the first thread from the first memory region.

23. The method of claim 19 , further including:

dedicating a third memory region to the objects associated with the first thread in response to a determination that the first memory region is full; and

conducting a second reclamation of the third memory region in response to the termination of the first thread.

24. The method of claim 19 , wherein the first and second threads correspond to the user interface activity.

Continuity (1)
Related Publication 20220171704A1 · Jun 2, 2022
References Cited (39)
US 6823518B1 · Bliss · 2004 [cited by examiner]
US 6842853B1 · Bush · 2005 [cited by examiner]
US 7945911B1 · Garthwaite · 2011 [cited by examiner]
US 10019341B2 · Ma · 2018 [cited by applicant]
US 20020049719A1 · Shiomi et al. · 2002 [cited by applicant]
US 20040158589A1 · Liang et al. · 2004 [cited by applicant]
US 20060074988A1 · Imanishi et al. · 2006 [cited by applicant]
US 20060085433A1 · Bacon · 2006 [cited by examiner]
US 20070169042A1 · Janczewski · 2007 [cited by examiner]
US 20080021939A1 · Dahlstedt · 2008 [cited by examiner]
US 20090083509A1 · Johnson · 2009 [cited by examiner]
US 20110252216A1 · Ylonen · 2011 [cited by examiner]
CN 1761949A · 2006 [cited by applicant]
CN 108073520A · 2018 [cited by applicant]
JP H04142867A · 1992 [cited by applicant]
JP 2002259146A · 2002 [cited by applicant]
JP 2004078636A · 2004 [cited by applicant]
JP 2009037546A · 2009 [cited by applicant]
JP 2011134202A · 2011 [cited by applicant]
WO 2009040228A1 · 2009 [cited by applicant]
WO 2016097680A1 · 2016 [cited by applicant]
WO 2017053109A1 · 2017 [cited by applicant]
WO 2018152229A1 · 2018 [cited by applicant]
International Search Report and Written Opinion for International Patent Application No. PCT/CN2019/089503, mailed Feb. 28, 2020, 8 pages. [cited by applicant]
Ankit Bisht, “Stack vs Heap Memory Allocation”, <geeksforgeeks.org/stack-vs-heap-memory-allocation/>, retrieved May 15, 2019, 4 pages. [cited by applicant]
Ahmed Hussein et al., “Impact of GC Design on Power and Performance for Android”, SYSTOR, ACM, May 26, 2015, 12 pages, Halfa Israel. [cited by applicant]
Sangmin Lee, “Understanding Java Garbage Collection”, <cubrid.org/blog/understanding-java-garbage-collection>, May 31, 2017, 15 pages. [cited by applicant]
F. Pizlo et al., “Real-Time Java Scoped Memory: Design Patterns and Semantics”, Seventh IEEE International Symposium on Object-Oriented Real-Time Distributed Computing, May 2004, 10 pages, Vienna, Austria. [cited by applicant]
International Searching Authority, “International Preliminary Report on Patentability,” issued in connection with International Patent Application No. PCT/CN2019/089503, issued on Nov. 16, 2021, 4 pages. [cited by applicant]
European Patent Office, “Extended European Search Report,” issued in connection with European Patent Application No. 19931226.5, dated Dec. 7, 2022, 9 pages. [cited by applicant]
European Patent Office, “Communication Under Rule 71(3) EPC,” issued in connection with European Patent Application No. 19931226.5, dated Apr. 17, 2024, 6 pages. [cited by applicant]
European Patent Office, “Decision to Grant a European Patent Pursuant to Article 97(1) EPC,” issued in connection with European Patent Application No. 19931226.5, dated Aug. 16, 2024, 2 pages. [cited by applicant]
Japan Patent Office, “Search Report by Registered Search Organization,” issued in connection with Japanese Patent Application No. 2021-563430, dated May 18, 2023, 40 pages. [With English Translation]. [cited by applicant]
Japan Patent Office, “Notice of Reasons for Refusal,” issued in connection with Japanese Patent Application No. 2021-563430, dated Jun. 20, 2023, 6 pages. [With English Translation]. [cited by applicant]
Japan Patent Office, “Notice of Reasons for Refusal,” issued in connection with Japanese Patent Application No. 2021-563430 dated Dec. 12, 2023, 6 pages. [With English Translation]. [cited by applicant]
Japan Patent Office, “Decision of Refusal,” issued in connection with Japanese Patent Application No. 2021-563430, dated May 28, 2024, 4 pages. [With English Translation]. [cited by applicant]
Japan Patent Office, “Decision of Dismissal of Amendment,” issued in connection with Japanese Patent Application No. 2021-563430, dated May 28, 2024, 5 pages. [With English Translation]. [cited by applicant]
Japan Patent Office, “Reconsideration Report by Examiner before Appeal,” issued in connection with Japanese Patent Application No. 2021-563430, dated Jan. 15, 2025, 4 pages. [With English Translation]. [cited by applicant]
Japan Patent Office, “Notice of Reasons for Refusal,” issued in connection with Japanese Patent Application No. 2021-563430, dated Jul. 10, 2025, 7 pages. [With English Translation]. [cited by applicant]